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Re: powerpc & unaligned block moves with fp registers
- To: degger at fhm dot edu
- Subject: Re: powerpc & unaligned block moves with fp registers
- From: mike stump <mrs at windriver dot com>
- Date: Sun, 11 Nov 2001 07:07:35 -0800 (PST)
- Cc: gcc at gcc dot gnu dot org
> From: email@example.com
> Date: Sun, 11 Nov 2001 00:23:15 +0100 (CET)
> Ok, I take my "on any cost" back. -Os is of course a different
> picture, when optimising for size alignment doesn't play such a big
> role. Anyway the mentioned cases are pretty rare (at least I haven't
> seen much wrongly aligned structures here in the past) and thusly I
> also think that aligning them properly would make such a big
> different in code size.
And next, tell us what the performance would be if 98.3% of all
dynamic loads were aligned just right, and the remainder were not in a
typical large application, and the same stat for a smallish
If the size decrease improves the instruction cache, and most of the
dynamic cases run fast anyway, would it not be possible for the code
to be actually slow if we followed your recommendation, even in the
non -Os case? If not, why not?
Also, what is the typical non-aligned hit rate in a large suit of
benchmarks? 1.7%, lower, higher?
Anyway... I ask all there questions, to try and help ensure that as
we make changes in this area, that we don't just make them blindly (in
the absence of real benchmarking data).