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Re: powerpc & unaligned block moves with fp registers
- To: mrs at windriver dot com
- Subject: Re: powerpc & unaligned block moves with fp registers
- From: degger at fhm dot edu
- Date: Sun, 11 Nov 2001 17:41:46 +0100 (CET)
- Cc: gcc at gcc dot gnu dot org
- Reply-to: degger at fhm dot edu
On 11 Nov, mike stump wrote:
> And next, tell us what the performance would be if 98.3% of all
> dynamic loads were aligned just right, and the remainder were not in a
> typical large application, and the same stat for a smallish
This cries for some heuristics which decides that some structure is
likely to be accessed more often and thus possible more critical
to performance due to many accesses.
> If the size decrease improves the instruction cache, and most of the
> dynamic cases run fast anyway, would it not be possible for the code
> to be actually slow if we followed your recommendation, even in the
> non -Os case? If not, why not?
This is not an easy decision and for sure one I wouldn't want to enforce
globally for the whole compiler. Also the amount of effect depends very
much on the complete system; the CPU, the amount of memory and cache and
even the operation mode of the CPU. Maybe it would be possible to
implement some feedback optimisation that doesn't just instrument the
iteration count of some codeblock but also the effect on the current
CPU including the cachemisses. Of course is not a good general approach
but would be a start to tell the compiler "optimize the software for a
machine close or equal to this one".
> Also, what is the typical non-aligned hit rate in a large suit of
> benchmarks? 1.7%, lower, higher?
No idea, I'll leave that up to the benchmark guys.
> Anyway... I ask all there questions, to try and help ensure that as
> we make changes in this area, that we don't just make them blindly (in
> the absence of real benchmarking data).
Yes, this looks like a sane idea and I appreciate your efforts to keep
me away from dreaming of an ideal world. :)