Register Coalescing

["Jon Beniston" <jbeniston at compxs dot com>]

Hi all,

I am having a few problems with what appears to be a lack of register
coalescing on a new GCC port I'm working on. For the following code:

int add(int a, int b)
{
    return b+a;
}

This is produced:

add      r5, r5, r4
mv       r4, r5
b        ra

Obviously, the optimal sequence would be:

add      r4, r5, r4
b        ra

I originally thought that this was probably something I was doing wrong
in my back-end, but I compiled the same code for ARM, and got:

add     r1, r1, r0
mov     r0, r1
mov     pc, lr

Which looks to me like the same problem. Can anyone offer any pointers
as to what might be the problem, or how I can track this down? I'm
working with the 3.2.3 source.

Cheers,
JonB