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Re: Register Coalescing
- From: Ian Lance Taylor <ian at wasabisystems dot com>
- To: <jbeniston at compxs dot com>
- Cc: <gcc at gcc dot gnu dot org>
- Date: 13 Jan 2004 09:36:48 -0500
- Subject: Re: Register Coalescing
- References: <002201c3d9bf$af445da0$06bda8c0@Kindrogan>
"Jon Beniston" <jbeniston@compxs.com> writes:
> I am having a few problems with what appears to be a lack of register
> coalescing on a new GCC port I'm working on. For the following code:
>
> int add(int a, int b)
> {
> return b+a;
> }
>
> This is produced:
>
> add r5, r5, r4
> mv r4, r5
> b ra
>
> Obviously, the optimal sequence would be:
>
> add r4, r5, r4
> b ra
>
> I originally thought that this was probably something I was doing wrong
> in my back-end, but I compiled the same code for ARM, and got:
>
> add r1, r1, r0
> mov r0, r1
> mov pc, lr
>
> Which looks to me like the same problem. Can anyone offer any pointers
> as to what might be the problem, or how I can track this down? I'm
> working with the 3.2.3 source.
I recommend that you try this patch, which is on the mainline but not
in 3.2.3:
2003-04-16 J"orn Rennecke <joern.rennecke@superh.com>
Re-apply this patch:
2002-05-16 Dale Johannesen <dalej@apple.com>
* combine.c (cant_combine_insn_p): Reenable combinations
involving hard regs unless CLASS_LIKELY_SPILLED_P.
Ian