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Re: GCC DFA Scheduling Query
- From: Jim Wilson <wilson at specifixinc dot com>
- To: Pankaj Dev <panks11 at hotmail dot com>
- Cc: gcc at gcc dot gnu dot org, vmakarov at redhat dot com
- Date: 12 Sep 2003 00:05:18 -0700
- Subject: Re: GCC DFA Scheduling Query
- References: <Law10-F1123frGlloEf0000d3eb@hotmail.com>
On Thu, 2003-09-11 at 21:55, Pankaj Dev wrote:
> yes true, the FETCH AND DECODE UNIT can be excluded from the DFA
> representation but the WRITE BACK UNIT I think should be included since it
> is used at the end. For e.g.
I don't have sparclet pipeline info and don't have any special interest
in the sparclet processor, so I can't advise you on the best way to
write the sparclet DFA description.
If a load followed by an ALU instrution causes a stall, then certainly
you want to model that. If modeling the writeback unit is necessary to
describe it then you would want to do that. There may also be other
ways to describe it.
I see that the sparc/ultra1_2.md and sparc/ultra3.md files have support
for load writeback cycles. They don't model an actual writeback unit
though, they just conflict with the alu for a cycle. This is what I'd
expect to see to model this kind of issue.
--
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com