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Re: GCC DFA Scheduling Query
- From: "Pankaj Dev" <panks11 at hotmail dot com>
- To: wilson at specifixinc dot com
- Cc: gcc at gcc dot gnu dot org, vmakarov at redhat dot com
- Date: Fri, 12 Sep 2003 10:25:13 +0530
- Subject: Re: GCC DFA Scheduling Query
yes true, the FETCH AND DECODE UNIT can be excluded from the DFA
representation but the WRITE BACK UNIT I think should be included since it
is used at the end. For e.g.
After a load store instruction, if we schedule an ALU instruction in the
FETCH, ALU+LDU, LDU, WB
FETCH, ALU, WB
Now here the WB unit will have a conflict and if we do not include WB unit
in the description then the compiler will not take care of the WB UNIT
conflicts and will make the processor stall during the execution. If at this
point some other ready instruction is availablethen compiler could schedule
I just wanted to be sure, if the above understanding is the approach to be
followed for the understanding of the DFA description.
From: Jim Wilson <email@example.com>
To: Pankaj Dev <firstname.lastname@example.org>
Subject: Re: GCC DFA Scheduling Query
Date: Wed, 10 Sep 2003 14:53:13 -0700
Pankaj Dev wrote:
I am actually curious about the DFA description of sparclet already in
I doubt that anyone has ever looked at this. This is just the obvious
translation of the old pre-DFA description into the new format. Since the
old one was a minimal description, the DFA description is also.
Since there is only one unit available for each FETCH AND DECODE and WRITE
BACK unit so I feel that they should also be included in the
insn_reservation description in the .md file.
This is very unlikely to do anything useful if you think about it. If
every instruction takes 1 cycle in the FETCH AND DECODE unit, then we don't
gain anything by modeling it because there is nothing to schedule.
The important thing here is how long it takes to execute instructions, and
other info is useful to model only if it affects execution time.
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com
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