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Re: load multiple
On Mon, Oct 14, 2002 at 07:36:24AM -0500, N V Krishna wrote:
> No. As I wrote before the only ldm instruction that I am seeing without
> consecutive registers is the last load to pop off registers and that
> instruction is inserted without using RTL.
You're not looking hard enough then. In particular, try some block moves.
(define_insn "*ldmsi4"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 2 "arm_hard_register_operand" "")
(mem:SI (match_operand:SI 1 "s_register_operand" "r")))
(set (match_operand:SI 3 "arm_hard_register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 4))))
(set (match_operand:SI 4 "arm_hard_register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 8))))
(set (match_operand:SI 5 "arm_hard_register_operand" "")
(mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
"TARGET_ARM && XVECLEN (operands[0], 0) == 4"
"ldm%?ia\\t%1, {%2, %3, %4, %5}"
[(set_attr "type" "load")
(set_attr "predicable" "yes")]
)
r~