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Re: load multiple
- From: N V Krishna <nvk at cs dot purdue dot edu>
- To: Richard Henderson <rth at redhat dot com>
- Cc: Andrew Haley <aph at redhat dot com>, <gcc at gnu dot org>
- Date: Tue, 15 Oct 2002 20:08:49 -0500 (EST)
- Subject: Re: load multiple
Hi,
On Tue, 15 Oct 2002, Richard Henderson wrote:
#You're not looking hard enough then. In particular, try some block moves.
Probably you are right.
#(define_insn "*ldmsi4"
# [(match_parallel 0 "load_multiple_operation"
# [(set (match_operand:SI 2 "arm_hard_register_operand" "")
# (mem:SI (match_operand:SI 1 "s_register_operand" "r")))
# (set (match_operand:SI 3 "arm_hard_register_operand" "")
# (mem:SI (plus:SI (match_dup 1) (const_int 4))))
# (set (match_operand:SI 4 "arm_hard_register_operand" "")
# (mem:SI (plus:SI (match_dup 1) (const_int 8))))
# (set (match_operand:SI 5 "arm_hard_register_operand" "")
# (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
# "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
# "ldm%?ia\\t%1, {%2, %3, %4, %5}"
# [(set_attr "type" "load")
# (set_attr "predicable" "yes")]
#)
#
I have seen this somewhere before do not remember the exact
place. I had tried something like the following before posting to the
newsgroup:
----
result = gen_rtx_PARALLEL (VOIDmode,
rtvec_alloc (2));
mem = gen_rtx_MEM (SImode, base_r));
RTX_UNCHANGING_P (mem) = 0;
MEM_IN_STRUCT_P (mem) = 0;
MEM_SCALAR_P (mem) = 1;
XVECEXP (result, 0, 0)
= gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, reg1), mem);
mem = gen_rtx_MEM (SImode, plus_constant(base_r,4));
RTX_UNCHANGING_P (mem) = 0;
MEM_IN_STRUCT_P (mem) = 0;
MEM_SCALAR_P (mem) = 1;
XVECEXP (result, 0, 1)
= gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, reg2), mem);
return result
---
If the registers reg1 and reg2 are consecutive registers then it works
out, otherwise it fails and the reason is simple : It seems the code above
is for instructions like :
ldmia base_r {reg1-reg2}.
But I want to do
ldmia base_r {reg1,reg2}.
Warm regards
Krishna