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Re: Subreg-byte patches (was: Branching for GCC 3.0)

On Tue, Jan 09, 2001 at 11:04:01AM +0100, Andreas Jaeger wrote:
> can you refresh my memory and explain what those patches are doing?
> What kind of operations (on registers) are enabled and why is this a
> pre requisite for Ultrasparc support?

SUBREG's second argument so far (SUBREG_WORD) used to mean for
non-paradoxical SUBREGs the "word count" either within a register
(in which case SUBREG_WORD 0 was the low part) or MEM (in which case
SUBREG_WORD 0 was the smallest memory address).

The major problem SPARC v9 has (there are other architectures with similar
problems) with this is that it is a 64bit architecture, thus WORD size is
64bits, but there are still 32bit registers (float SFmode registers), so
there were problems in expressing e.g. store of high 32bits of 64bit %f8
register) etc. I believe this was the main reason why David Miller and
Richard Henderson (somebody else as well?) decided in 1998 that this needs
to change.

SUBREG_BYTE patches change the meaning of the second SUBREG's argument to
SUBREG_BYTE, plus the meaning is unified between REGs and MEMs, ie.
SUBREG_BYTE 0 is always the lowest addressable part, as if you stored the
whole REG into memory. Thus, lowest 8 bits of some 64bit register on big
endian machine are (subreg:QI (reg:DI xx) 56).


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