[gcc(refs/users/meissner/heads/work235-dmf)] Update ChangeLog.*
Michael Meissner
meissner@gcc.gnu.org
Fri Jan 30 17:07:26 GMT 2026
https://gcc.gnu.org/g:31f3b38944023b548f41050f52d4e5cfeb23dfff
commit 31f3b38944023b548f41050f52d4e5cfeb23dfff
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Jan 29 23:33:26 2026 -0500
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.dmf | 253 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 253 insertions(+)
diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
index e1574cc9a063..d741302a4a35 100644
--- a/gcc/ChangeLog.dmf
+++ b/gcc/ChangeLog.dmf
@@ -1,3 +1,256 @@
+==================== Branch work235-dmf, patch #103 ====================
+
+Document mma instruction names.
+
+This is an optional patch. As I was updating the MMA support, I figured to add
+comments for the MMA insn patterns to say which instructions are created for
+each insn.
+
+2026-01-29 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/mma.md (mma_<vv>): Add comments saying which
+ instructions are supported by the insn.
+ (mma_<avv>): Likewise.
+ (mma_<pv>): Likewise.
+ (mma_<apv>): Likewise.
+ (mma_<vvi4i4i8>): Likewise.
+ (mma_<avvi4i4i8>): Likewise.
+ (mma_<vvi4i4i2>): Likewise.
+ (mma_<avvi4i4i2>): Likewise.
+ (mma_<vvi4i4>): Likewise.
+ (mma_<avvi4i4>): Likewise.
+ (mma_<pvi4i2>): Likewise.
+ (mma_<apvi4i2>): Likewise.
+ (mma_<vvi4i4i4>): Likewise.
+ (mma_<avvi4i4i4>): Likewise.
+
+==================== Branch work235-dmf, patch #102 ====================
+
+Add support for 1,024 bit dense math registers.
+
+This patch is a prelimianry patch to add the full 1,024 bit dense math register
+(DMRs) for -mcpu=future. The MMA 512-bit accumulators map onto the top of the
+DMR register.
+
+This patch only adds the new 1,024 bit register support. It does not add
+support for any instructions that need 1,024 bit registers instead of 512 bit
+registers.
+
+I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit
+registers. The 'wD' constraint added in previous patches is used for these
+registers. I added support to do load and store of DMRs via the VSX registers,
+since there are no load/store dense math instructions. I added the new keyword
+'__dm1024' to create 1,024 bit types that can be loaded into dense math
+registers.
+
+The patches have been tested on both little and big endian systems. Can I check
+it into the master branch?
+
+2026-01-29 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
+ (UNSPEC_DM_INSERT512_LOWER): Likewise.
+ (UNSPEC_DM_EXTRACT512): Likewise.
+ (UNSPEC_DM_RELOAD_FROM_MEMORY): Likewise.
+ (UNSPEC_DM_RELOAD_TO_MEMORY): Likewise.
+ (movtdo): New define_expand and define_insn_and_split to implement 1,024
+ bit dense math registers.
+ (movtdo_insert512_upper): New insn.
+ (movtdo_insert512_lower): Likewise.
+ (movtdo_extract512): Likewise.
+ (reload_tdo_from_memory): Likewise.
+ (reload_tdo_to_memory): Likewise.
+ * config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add dense math
+ register support.
+ (rs6000_init_builtins): Add support for __dm1024 keyword.
+ * config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support
+ for TDOmode.
+ (rs6000_function_arg): Likewise.
+ * config/rs6000/rs6000-modes.def (TDOmode): New mode.
+ * config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add
+ support for TDOmode.
+ (rs6000_hard_regno_mode_ok_uncached): Likewise.
+ (rs6000_hard_regno_mode_ok): Likewise.
+ (rs6000_modes_tieable_p): Likewise.
+ (rs6000_debug_reg_global): Likewise.
+ (rs6000_setup_reg_addr_masks): Likewise.
+ (rs6000_init_hard_regno_mode_ok): Add support for TDOmode. Setup reload
+ hooks for dense math TDO reload mode.
+ (reg_offset_addressing_ok_p): Add support for TDOmode.
+ (rs6000_emit_move): Likewise.
+ (rs6000_secondary_reload_simple_move): Likewise.
+ (rs6000_preferred_reload_class): Likewise.
+ (rs6000_mangle_type): Add mangling for __dm1024 type.
+ (rs6000_dense_math_register_move_cost): Add support for TDOmode.
+ (rs6000_split_multireg_move): Likewise.
+ (rs6000_invalid_conversion): Likewise.
+ * config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode.
+ (enum rs6000_builtin_type_index): Add dense math register type nodes.
+ (dm1024_type_node): Likewise.
+ (ptr_dm1024_type_node): Likewise.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/dm-1024bit.c: New test.
+ * lib/target-supports.exp (check_effective_target_ppc_dm1024_ok): New
+ target test.
+
+==================== Branch work235-dmf, patch #101 ====================
+
+Add support for dense math registers.
+
+The MMA subsystem added the notion of accumulator registers as an optional
+feature of ISA 3.1 (power10 and power11). In ISA 3.1, these accumulators
+overlapped with the VSX registers 0..31, but logically the accumulator registers
+were separate from the FPR registers. In ISA 3.1, it was anticipated that in
+future systems, the accumulator registers may no overlap with the FPR registers.
+This patch adds the support for dense math registers as separate registers.
+
+This patch updates the wD constraint added in the previous patch. If MMA is
+selected but dense math is not selected (i.e. -mcpu=power10), the wD constraint
+will allow access to accumulators that overlap with VSX registers 0..31. If
+both MMA and dense math are selected (i.e. -mcpu=future), the wD constraint
+will only allow dense math registers.
+
+This patch modifies the existing %A output modifier. If MMA is selected but
+dense math is not selected, then %A output modifier converts the VSX register
+number to the accumulator number, by dividing it by 4. If both MMA and dense
+math are selected, then %A will map the separate dense math registers into 0..7.
+
+The intention is that user code using extended asm can be modified to run on
+both MMA without dense math and MMA with dense math:
+
+ 1) If possible, don't use extended asm, but instead use the MMA built-in
+ functions;
+
+ 2) If you do need to write extended asm, change the d constraints
+ targetting accumulators should now use wD;
+
+ 3) Only use the built-in zero, assemble and disassemble functions create
+ move data between vector quad types and dense math accumulators.
+ I.e. do not use the xxmfacc, xxmtacc, and xxsetaccz directly in the
+ extended asm code. The reason is these instructions assume there is a
+ 1-to-1 correspondence between 4 adjacent FPR registers and an
+ accumulator that overlaps with those instructions. With accumulators
+ now being separate registers, there no longer is a 1-to-1
+ correspondence.
+
+It is possible that the mangling for dense math registers and the GDB register
+numbers may need to be changed in the future.
+
+gcc/
+
+2026-01-29 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/mma.md (UNSPEC_MMA_DMSETDMRZ): New unspec.
+ (movxo): Move comment about XOmode being restricted to FPRs to
+ movxo_mode.
+ (movxo_nodm): Rename from movxo and restrict the usage to machines
+ without dense math registers.
+ (movxo_dm): New insn for movxo support for machines with dense math
+ registers.
+ (mma_<acc>): Restrict usage to machines without dense math registers.
+ (mma_xxsetaccz): Add a define_expand wrapper, and add support for dense
+ math registers.
+ (mma_dmsetaccz): New insn.
+ (mma_<vv>): Add comment about MMA using or not using dense math
+ registers.
+ * config/rs6000/predicates.md (dense_math_operand): New predicate.
+ (accumulator_operand): Add support for dense math registers. Add
+ support for SUBREGs.
+ * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Do
+ not issue a de-prime instruction when disassembling a vector quad on a
+ system with dense math registers.
+ * config/rs6000/rs6000-c.cc (rs6000_define_or_undefine_macro): Define
+ __DENSE_MATH__ if we have dense math registers.
+ * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): Add -mdense-math.
+ (POWERPC_MASKS): Likewise.
+ * config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DM_REG_TYPE.
+ (enum rs6000_reload_reg_type): Add RELOAD_REG_DM.
+ (LAST_RELOAD_REG_CLASS): Add support for dense math registers and the wD
+ constraint.
+ (reload_reg_map): Likewise.
+ (rs6000_reg_names): Likewise.
+ (alt_reg_names): Likewise.
+ (rs6000_hard_regno_nregs_internal): Likewise.
+ (rs6000_hard_regno_mode_ok_uncached): Likewise.
+ (rs6000_debug_reg_global): Likewise.
+ (rs6000_setup_reg_addr_masks): Likewise.
+ (rs6000_init_hard_regno_mode_ok): Likewise.
+ (rs6000_option_override_internal): If -mdense-math, issue an error if
+ not -mcpu=future.
+ (rs6000_secondary_reload_memory): Add support for dense math registers.
+ (rs6000_secondary_reload_simple_move): Likewise.
+ (rs6000_preferred_reload_class): Likewise.
+ (rs6000_secondary_reload_class): Likewise.
+ (print_operand): Make %A handle both dense math registers or FPRs
+ depending on whether dense registers are available.
+ (rs6000_dense_math_register_move_cost): New helper function.
+ (rs6000_register_move_cost): Add support for dense math registers.
+ (rs6000_memory_move_cost): Likewise.
+ (rs6000_compute_pressure_classes): Likewise.
+ (rs6000_debugger_regno): Likewise.
+ (rs6000_opt_masks): Add -mdense-math support.
+ (rs6000_split_multireg_move): Add support for dense math registers.
+ * config/rs6000/rs6000.h (UNITS_PER_DM_WORD): Likewise.
+ (FIRST_PSEUDO_REGISTER): Update for dense math registers.
+ (FIXED_REGISTERS): Add dense math registers.
+ (CALL_REALLY_USED_REGISTERS): Likewise.
+ (REG_ALLOC_ORDER): Likewise.
+ (DM_REGNO_P): New macro.
+ (enum reg_class): Add DM_REGS.
+ (REG_CLASS_NAMES): Likewise.
+ (REG_CLASS_CONTENTS): Likewise.
+ (enum r6000_reg_class_enum): Add RS6000_CONSTRAINT_wD.
+ (REGISTER_NAMES): Add dense math registers.
+ (ADDITIONAL_REGISTER_NAMES): Likewise.
+ * config/rs6000/rs6000.md (FIRST_DM_REGNO): New constant.
+ (LAST_DM_REGNO): Likewise.
+ * config/rs6000/rs6000.opt (-mdense-math): New option.
+ * doc/invoke.texi (RS/6000 and PowerPC Options): Add -mdense-math.
+
+==================== Branch work235-dmf, patch #100 ====================
+
+Add wD constraint.
+
+This patch adds a new constraint ('wD') that matches the accumulator registers
+that overlap with VSX registers 0..31 on power10. Future patches will add the
+support for a separate accumulator register class that will be used when the
+support for dense math registes is added.
+
+2026-01-29 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/constraints.md (wD): New constraint.
+ * config/rs6000/mma.md (mma_<acc>): Prepare for alternate accumulator
+ registers. Use wD constraint instead of 'd' constraint. Use
+ accumulator_operand instead of fpr_reg_operand.
+ (mma_<vv>): Likewise.
+ (mma_<avv>): Likewise.
+ (mma_<pv>): Likewise.
+ (mma_<apv>): Likewise.
+ (mma_<vvi4i4i8>): Likewise.
+ (mma_<avvi4i4i8>): Likewise.
+ (mma_<vvi4i4i2>): Likewise.
+ (mma_<avvi4i4i2>): Likewise.
+ (mma_<vvi4i4>): Likewise.
+ (mma_<avvi4i4>): Likewise.
+ (mma_<pvi4i2): Likewise.
+ (mma_<apvi4i2>): Likewise.
+ (mma_<vvi4i4i4>): Likewise.
+ (mma_<avvi4i4i4): Likewise.
+ * config/rs6000/predicates.md (accumulator_operand): New predicate.
+ * config/rs6000/rs6000.cc (rs6000_debug_reg_global): Print the register
+ class for the 'wD' constraint.
+ (rs6000_init_hard_regno_mode_ok): Set up the 'wD' register constraint
+ class.
+ * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add element for
+ the 'wD' constraint.
+ * doc/md.texi (PowerPC constraints): Document the 'wD' constraint.
+
==================== Branch work235-dmf, baseline ====================
2026-01-29 Michael Meissner <meissner@linux.ibm.com>
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