[gcc(refs/users/meissner/heads/work235-dmf)] Document mma instruction names.

[Michael Meissner]

https://gcc.gnu.org/g:0bcfaf05a47733fe05c66b7ec1ef8a4dd523e84e

commit 0bcfaf05a47733fe05c66b7ec1ef8a4dd523e84e
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Jan 29 23:27:11 2026 -0500

    Document mma instruction names.
    
    This is an optional patch.  As I was updating the MMA support, I figured to add
    comments for the MMA insn patterns to say which instructions are created for
    each insn.
    
    2026-01-29   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/mma.md (mma_<vv>): Add comments saying which
            instructions are supported by the insn.
            (mma_<avv>): Likewise.
            (mma_<pv>): Likewise.
            (mma_<apv>): Likewise.
            (mma_<vvi4i4i8>): Likewise.
            (mma_<avvi4i4i8>): Likewise.
            (mma_<vvi4i4i2>): Likewise.
            (mma_<avvi4i4i2>): Likewise.
            (mma_<vvi4i4>): Likewise.
            (mma_<avvi4i4>): Likewise.
            (mma_<pvi4i2>): Likewise.
            (mma_<apvi4i2>): Likewise.
            (mma_<vvi4i4i4>): Likewise.
            (mma_<avvi4i4i4>): Likewise.

Diff:
---
 gcc/config/rs6000/mma.md | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 132ed2f9c5c9..a1f05821d857 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -548,6 +548,10 @@
 ;; If dense math registers are not available, these operations will use
 ;; accumulators that are overlaid on top of the FPR registers.
 
+;; Instructions:
+;; xvi4ger8   xvi8ger4 xvi16ger2 xvi16ger2s xvf16ger2
+;; xvbf16ger2 xvf32ger
+
 (define_insn "mma_<vv>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
@@ -557,6 +561,12 @@
   "<vv> %A0,%x1,%x2"
   [(set_attr "type" "mma")])
 
+;; Instructions:
+;; xvi4ger8pp   xvi8ger4pp  xvi8ger4spp   xvi16ger2pp xvi16ger2spp
+;; xvf16ger2pp  xvf16ger2pn  xvf16ger2np  xvf16ger2nn xvbf16ger2pp
+;; xvbf16ger2pn xvbf16ger2np xvbf16ger2nn xvf32gerpp  xvf32gerpn
+;; xvf32gernp   xvf32gernn
+
 (define_insn "mma_<avv>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
@@ -567,6 +577,8 @@
   "<avv> %A0,%x2,%x3"
   [(set_attr "type" "mma")])
 
+;; Instruction: xvf64ger
+
 (define_insn "mma_<pv>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
@@ -576,6 +588,8 @@
   "<pv> %A0,%x1,%x2"
   [(set_attr "type" "mma")])
 
+;; Instructions: xvf64gerpp xvf64gerpn xvf64gernp xvf64gernn
+
 (define_insn "mma_<apv>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
@@ -586,6 +600,8 @@
   "<apv> %A0,%x2,%x3"
   [(set_attr "type" "mma")])
 
+;; Instruction: pmxvi4ger8
+
 (define_insn "mma_<vvi4i4i8>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
@@ -599,6 +615,8 @@
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
+;; Instruction: pmxvi4ger8pp
+
 (define_insn "mma_<avvi4i4i8>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
@@ -613,6 +631,9 @@
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
+;; Instructions:
+;; pmxvi16ger2 pmxvi16ger2s pmxvf16ger2 pmxvbf16ger2
+
 (define_insn "mma_<vvi4i4i2>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
@@ -626,6 +647,11 @@
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
+;; Instructions:
+;; pmxvi16ger2pp  pmxvi16ger2spp pmxvf16ger2pp  pmxvf16ger2pn
+;; pmxvf16ger2np  pmxvf16ger2nn  pmxvbf16ger2pp pmxvbf16ger2pn
+;; pmxvbf16ger2np pmxvbf16ger2nn
+
 (define_insn "mma_<avvi4i4i2>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
@@ -640,6 +666,8 @@
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
+;; Instruction: pmxvf32ger
+
 (define_insn "mma_<vvi4i4>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
@@ -652,6 +680,8 @@
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
+;; Instructions: pmxvf32gerpp pmxvf32gerpn pmxvf32gernp pmxvf32gernn
+
 (define_insn "mma_<avvi4i4>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
@@ -665,6 +695,8 @@
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
+;; Instruction: pmxvf64ger
+
 (define_insn "mma_<pvi4i2>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
@@ -677,6 +709,8 @@
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
+;; Instructions: pmxvf64gerpp pmxvf64gerpn pmxvf64gernp pmxvf64gernn
+
 (define_insn "mma_<apvi4i2>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
@@ -690,6 +724,8 @@
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
+;; Instruction: pmxvi8ger4
+
 (define_insn "mma_<vvi4i4i4>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
@@ -703,6 +739,8 @@
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
+;; Instructions: pmxvi8ger4pp pmxvi8ger4spp
+
 (define_insn "mma_<avvi4i4i4>"
   [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
 	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")