This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: Register constraints + and =


On May 9, 2012, at 5:34 AM, Paulo J. Matos wrote:

> On 08/05/12 21:57, Jan Hubicka wrote:
>> 
>> In expanded form it is
>> 
>>  (set (reg5) (const 10))
>> 
>>  (parallel [(set (reg2) (const 0))
>>            (set (reg0) (plus (reg3) (reg5)))
>>            (set (reg1) (plus (reg4) (reg5)))
>>            (set (mem (reg3)) (mem (reg4)))])
>> 
>>  (set (reg0) (plus (reg0) (const 10)))
>> 
>>  (set (reg1) (plus (reg1) (const 10)))
>> 
>> instructions separated by empty lines.
>> 
> 
> 
> Jan,
> why do you need the two sets after the parallel? Aren't those sets repeating what the parallel is already doing? They look like they are doing the same as the second and third insn in the parallel.
> 

He was showing the RTL expansion of the example he gave:

>> 
>> 
>> So seeing something like
>> 
>> memcpy(DX,SX,10)
>> DX+=10
>> SX+=10
>> 
>> is IMO foldable to
>> 
>> memcpy(DX,SX,20)
> 
The two extra sets are for the two statements after the memcpy, and the concern is that the optimizer (a future optimizer) could fold that and mess up the intent.

	paul


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]