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Re: Register constraints + and =

On 08/05/12 21:57, Jan Hubicka wrote:

In expanded form it is

(set (reg5) (const 10))

  (parallel [(set (reg2) (const 0))
            (set (reg0) (plus (reg3) (reg5)))
            (set (reg1) (plus (reg4) (reg5)))
            (set (mem (reg3)) (mem (reg4)))])

(set (reg0) (plus (reg0) (const 10)))

(set (reg1) (plus (reg1) (const 10)))

instructions separated by empty lines.

why do you need the two sets after the parallel? Aren't those sets repeating what the parallel is already doing? They look like they are doing the same as the second and third insn in the parallel.

If the aim is to have reg0 / reg1 pointing just past the size of the buffer (in reg5), then I can't understand the above instructions. Can you please clarify?

This is what I see.
If the buffer has size 10, the above will translate to:
>   (set (reg5) (const 10))

Count is set to 10.

>   (parallel [(set (reg2) (const 0))
>             (set (reg0) (plus (reg3) (reg5)))
>             (set (reg1) (plus (reg4) (reg5)))
>             (set (mem (reg3)) (mem (reg4)))])

After the parallel reg2 (allocated to same as reg5) is set to 0.
reg0 (allocated to same as reg3) is pointing to end of destination buffer (reg0 = reg0 + 10). reg1 (allocated to same as reg4) is pointing to end of source buffer (reg1 = reg4 + 10). Last insn represents the copy of the memory contents.

>   (set (reg0) (plus (reg0) (const 10)))

This will set reg0 to point 10 past the end of the buffer (20 past the start of the buffer), which seems to be too far.

>   (set (reg1) (plus (reg1) (const 10)))

Same as above for reg0. Seems to end up too far from end of buffer.


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