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Re: Porting new target architecture to GCC
- From: Alexander Monakov <amonakov at ispras dot ru>
- To: Ben Morgan <benm dot morgan at gmail dot com>
- Cc: gcc at gcc dot gnu dot org
- Date: Wed, 2 May 2012 16:21:56 +0400 (MSK)
- Subject: Re: Porting new target architecture to GCC
- References: <4FA11ACB.firstname.lastname@example.org>
On Wed, 2 May 2012, Ben Morgan wrote:
> In a course at my university (UniversitÃt WÃrzburg, Germany) we have
> created a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL)
> which we then play onto a FPGA (the Xilinx Spartan-3AN) to use. So far
> if we want to do anything with it, we have to write the assembly code
> How much work would it be to write a HadesXI backend for GCC?
I remember "6 months and more of full-time work for a skilled developer"
mentioned on this mailing list.
> Where would be a good place to start; what are the prerequisites for
> undertaking a project like this other than knowing the CPU architecture
> inside out?
I recommend reading "The GGX patch archive" blog entries to get a "big
picture" of the steps involved. It was available at spindazzle.org/ggx,
but at the moment you'll have to browse it via The Internet Archive
( http://web.archive.org/web/20100117171845/http://spindazzle.org/ggx/ ).
Apart from that, the GCC wiki has accumulated many resources, especially
in the GettingStarted section ( http://gcc.gnu.org/wiki/GettingStarted ).