This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: IRA issue with shuffle copies...


On 01/10/2012 12:55 PM, Peter Bergner wrote:
On Tue, 2012-01-10 at 12:20 -0500, Vladimir Makarov wrote:
Do we really need or want to create shuffle copies for insns that do not
have a two operand constraint?
Yes, I think so.  As I remember I did some benchmarking and it gave some
"order" in hard register assignments and improved code slightly (at
least for SPEC2000) even for 3-ops insn architectures.

Ok, I'll have someone on my team kick off this patch on ppc, but it would be nice if someone else could do the runs on x86/x86_64 or other cpus that might be affected that we don't have access to.

There is no visible effect of the patch on SPECFP2000 performance and size (the size increase is only about 0.02%) for x86 and x86-64.

The patch does worsen performance of SPECINT2000 on x86 (about 0.5%) and x86-64 (about 0.3%). x86-64 SPECINT200 code size increase is about 0.05% and there is no visible change in code size on x86.

So I'd say the patch does not work for x86/x86-64.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]