This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: Question about Machine Description


Hi,

I want to change instruction blez to ble. ble compare two registers and jump
to the target address if the condition is true.

thanks in advance,

Ian Lance Taylor-3 wrote:
> 
> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
> 
>> Please assume I'm working with the MIPS. There is a little difference
>> between the MIPS and what I'm actually working on it. How can I remove
>> immediate logical shift right/left from the compiler?
>> I mean If I want the programmer writes an immediate shift, It is compiled
>> to
>> the two instructions:
>>
>> sll %2,%2,5
>>
>> changed to:
>>
>> addi %3,%0,5
>> sllv %2,%2,%3
> 
> Find the insn which generates sll.  Change the operand constraints and
> predicates to reject an immediate operand.
> 
> E.g., in mips.md this is:
> 
> (define_insn "*<optab><mode>3"
>   [(set (match_operand:GPR 0 "register_operand" "=d")
> 	(any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
> 		       (match_operand:SI 2 "arith_operand" "dI")))]
>   "!TARGET_MIPS16"
> {
>   if (CONST_INT_P (operands[2]))
>     operands[2] = GEN_INT (INTVAL (operands[2])
> 			   & (GET_MODE_BITSIZE (<MODE>mode) - 1));
> 
>   return "<d><insn>\t%0,%1,%2";
> }
>   [(set_attr "type" "shift")
>    (set_attr "mode" "<MODE>")])
> 
> 
> For operand 2, change the predicate to register_operand and remove the
> 'I' constraint.
> 
> Ian
> 
> 

-- 
View this message in context: http://old.nabble.com/Question-about-Machine-Description-tp1026428p28447744.html
Sent from the gcc - Dev mailing list archive at Nabble.com.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]