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SH: PR target/24445
- From: Kaz Kojima <kkojima at rr dot iij4u dot or dot jp>
- To: gcc at gcc dot gnu dot org
- Cc: joern dot rennecke at st dot com, aoliva at redhat dot com
- Date: Thu, 03 Nov 2005 08:10:12 +0900 (JST)
- Subject: SH: PR target/24445
Hi,
I've tried to see what is gonig on for PR target/24445 which is
a 4.1 regression of SH.
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=24445
Comparing rtl dumps for the reduced testcase in the audit trail #4
of that PR with and without Jan's patch in #10, there is no return
value copy in the rtl generated with the patched compiler in the first
place.
[.expand after the patch]
(set (reg/f:SI 160) (const:SI (unspec [(symbol_ref:SI ("baz"))] 7)))
(set (reg:SI 161) (plus:SI (reg:SI 12 r12) (reg/f:SI 160)))
(set (reg/f:SI 159) (mem/u/c:SI (reg:SI 161)))
(set (reg:SI 0 r0) (call (mem:SI (symbol_ref:SI ("bar")))))
(set (mem/c/i:SI (reg/f:SI 159)) (reg:SI 0 r0)))
[.expand before the patch]
(set (reg/f:SI 160) (const:SI (unspec [(symbol_ref:SI ("baz"))] 7)))
(set (reg:SI 161) (plus:SI (reg:SI 12 r12) (reg/f:SI 160)))
(set (reg/f:SI 159) (mem/u/c:SI (reg:SI 161)))
(set (reg:SI 0 r0) (call (mem:SI (symbol_ref:SI ("bar")))))
(set (reg:SI 164) (reg:SI 0 r0))
(set (mem/c/i:SI (reg/f:SI 159)) (reg:SI 164))
The 2nd and 3rd insns are combined to
(set (reg/f:SI 159) (mem/u/c:SI (plus:SI (reg:SI 12 r12) (reg/f:SI 160))))
at the combine pass.
An optimization in local-alloc moves the PLT address calculation after
the function call:
[.lreg after the patch]
(set (reg:SI 0 r0) (call (mem:SI (symbol_ref:SI ("bar")))))
(set (reg/f:SI 160) (const:SI (unspec [(symbol_ref:SI ("baz"))] 7)))
(set (reg/f:SI 159) (mem/u/c:SI (plus:SI (reg:SI 12 r12) (reg/f:SI 160))))
(set (mem/c/i:SI (reg/f:SI 159)) (reg:SI 0 r0)))
[.lreg before the patch]
(set (reg:SI 0 r0) (call (mem:SI (symbol_ref:SI ("bar")))))
(set (reg:SI 164) (reg:SI 0 r0))
(set (reg/f:SI 160) (const:SI (unspec [(symbol_ref:SI ("baz"))] 7)))
(set (reg/f:SI 159) (mem/u/c:SI (plus:SI (reg:SI 12 r12) (reg/f:SI 160))))
(set (mem/c/i:SI (reg/f:SI 159)) (reg:SI 164))
Then the reload pass complains that r0 can't be allocated to pseudo
160 in the former case because r0 is the unique index register of SH.
I don't understand which part is problematic, though. How this PR
should be fixed?
Regards,
kaz