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Predicated execution / if-conversion?
- From: "Jan Hoogerbrugge" <hoogerbrugge at hotmail dot com>
- To: gcc at gcc dot gnu dot org
- Date: Wed, 21 Jan 2004 16:33:33 +0100
- Subject: Predicated execution / if-conversion?
- Bcc:
Hi,
My target processor supports predicated execution so I want to
exploit this. Like conditional branches in my architecture,
prediction works on the least significant bit of a register.
So I have to use BImode for the result of compare operations.
Could somebody tell me how to start with modelling predicated
execution? With a few exceptions, all operations can be
predicated. I noticed that the FRV port defines the IFCVT
macros. Is that necessary or only to model more complex cases?
What do I have to do in the .md file? Are there ports that
I should study? I noticed "%," and current_insn_predicate
in the ia64 port. How does this work?
Thanks,
Jan
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