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Re: mainline -mcpu=power4
Alan Modra <amodra@bigpond.net.au> writes:
> On Wed, Jan 07, 2004 at 04:40:15PM -0800, Geoff Keating wrote:
> > Alan Modra <amodra@bigpond.net.au> writes:
> > > Hmm, -mcpu=power4 leaves MASK_POWERPC64 off in target_flags, so
> > > UNITS_PER_WORD is 4 and HARD_REGNO_NREGS thinks we need two regs for
> > > DI:lr
> > >
> > > What's the right fix here? Using TARGET_64BIT in the insn predicate
> > > doesn't agree with using TARGET_POWERPC64 (indirectly) in
> > > HARD_REGNO_NREGS.
> >
> > Add TARGET_POWERPC64 to this line:
> >
> > {"power4", PROCESSOR_POWER4, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
> >
> > I forgot that POWER4 was also a 64-bit processor.
>
> Yes, that's the obvious fix to make -mcpu=power4 work. I was really
> asking about why we have TARGET_64BIT in the insn predicate. It's a
> rather more general problem than just fixing -mcpu=power4. For
> instance, -m64 -mcpu=601 gets the ICE too.
TARGET_64BIT basically means that the chip is running in "64-bit
mode", in which pointers are 64 bits, CR0 is set in dot operations
based on all 64 bits of the register, bdnz works on 64-bit counters, and
so on, and in particular return addresses are 64 bits. Therefore, we
must use DImode in the return pattern when TARGET_64BIT, and SImode
when TARGET_32BIT, and it doesn't make sense to have them both active
at the same time.
It's correct (well, not optimal, but correct) to ICE when you say -m64
-mcpu=601. You've asked GCC to generate code for 64-bit pointers, but
you have told it to do this on a processor that does not have any
64-bit instructions; GCC cannot do this, thus the ICE. It'd probably
be better to print some nice error message, but it's certainly an
error condition.
--
- Geoffrey Keating <geoffk@geoffk.org>