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Re: RFC: Improve MIPS code generation.

From: David Daney <ddaney at avtrex dot com>
To: Daniel Jacobowitz <drow at mvista dot com>
Cc: gcc at gcc dot gnu dot org
Date: Fri, 03 Oct 2003 15:23:49 -0700
Subject: Re: RFC: Improve MIPS code generation.
References: <3F7DF470.7010802@avtrex.com> <20031003221722.GA18394@nevyn.them.org>

Daniel Jacobowitz wrote:

On Fri, Oct 03, 2003 at 03:13:04PM -0700, David Daney wrote:
Recently I have been thinking about gcc's code generation especially
WRT the MIPS o32 ABI, but I think that the ideas might be relevant to
other architectures as well.
I am not quite sure how to implement this, but wanted to get feedback.
FYI, Alpha already implements this.  It's done more effectively as a
linker optimization and takes a fair bit of code.

But the compiler can (and does) move the load of the JALR target register away from the JALR, which would make it very difficult for the linker to convert it into a BAL.

Follow-Ups:
- Re: RFC: Improve MIPS code generation.
  - From: Daniel Jacobowitz
- Re: RFC: Improve MIPS code generation.
  - From: Alexandre Oliva

References:
- RFC: Improve MIPS code generation.
  - From: David Daney
- Re: RFC: Improve MIPS code generation.
  - From: Daniel Jacobowitz

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