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Re: inline asm constraints for conditions
- From: Richard Henderson <rth at redhat dot com>
- To: David Howells <dhowells at redhat dot com>
- Cc: gcc at gcc dot gnu dot org
- Date: Fri, 26 Sep 2003 13:39:35 -0700
- Subject: Re: inline asm constraints for conditions
- References: <email@example.com>
On Fri, Sep 26, 2003 at 07:07:12PM +0100, David Howells wrote:
> Would it be possible to get a new type of inline asm constraint added, such
> that a "condition" can be an output?
Not like this, no.
The most basic problem for x86 is that the flags register dies too often.
If we were to add the ability for it to live longer and be reloaded (say
with lahf/sahf), then generic parts of the compiler would start trying to
make use of it, which would almost certainly result in worse code overall
even when the feature was not in use.
> As for non-x86 CPUs, on something like the SH where, IIRC, you have a single
> flag (T), the following would then be possible:
> "=?t/f" or "=?f/t"
> And on the IA64 where predicate registers are available:
For ia64, this ought to be possible. On ia64 you'd use a constraint
of "=c", which would imply the pair (pN,pN+1) for N even. The one
missing piece is that there is no language-level access to a BImode
type. Something that I've been meaning to try for a while is to
arrange for "bool" to have BImode and see what happens...
For sh, I suspect there will be similar problems as with x86, though
not as bad because fewer instructions clobber T. It would definitely
have similar problems as ia64 wrt BImode.