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Re: An unusual Performance approach using Synthetic registers
On Tuesday 07 January 2003 11:26 pm, Andy Walker wrote:
> On Tuesday 07 January 2003 10:18 am, Michael S. Zick wrote:
> > It has always done its register <-> memory thing correctly.
>
> Thank you for the info. This is _not_ in the XCHG description in the Intel
> Developer's manuals.
>
Good catch - It is always good to check anything I say for errors.
>
> ok. for now. :o)
> dumb statistic, fwiw: dual processor 500Mhz Celerons.
> My Mandrake 8.2 distro calls it a pentiumpro.
>
So lets try to focus on the model you have - We can generalize later.
Go to your /var/log/dmesg file, post your part that corresponds to this:
- - - snip - - -
CPU: Before vendor init, caps: 0383fbff 00000000 00000000, vendor = 0
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 512K
CPU: After vendor init, caps: 0383fbff 00000000 00000000 00000000
Intel machine check reporting enabled on CPU#0.
CPU: After generic, caps: 0383fbff 00000000 00000000 00000000
CPU: Common caps: 0383fbff 00000000 00000000 00000000
CPU0: Intel(R) Pentium(R) III CPU family 1266MHz stepping 01
- - - snip - - -
CPU: Before vendor init, caps: 0383fbff 00000000 00000000, vendor = 0
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 512K
CPU: After vendor init, caps: 0383fbff 00000000 00000000 00000000
Intel machine check reporting enabled on CPU#1.
CPU: After generic, caps: 0383fbff 00000000 00000000 00000000
CPU: Common caps: 0383fbff 00000000 00000000 00000000
CPU1: Intel(R) Pentium(R) III CPU family 1266MHz stepping 01
Total of 2 processors activated (5052.82 BogoMIPS).
- - - snip - - -
The "caps:" is the encoded chip features, gives us a little focus.
Mike
> Andy