Re: An unusual Performance approach using Synthetic registers

[Andy Walker <ja_walker at earthlink dot net>]

On Tuesday 07 January 2003 10:18 am, Michael S. Zick wrote:
> On Tuesday 07 January 2003 06:47 am, Robert Dewar wrote:
> > I had thought that these instructions were only available on recent
> > chips, so if they are used you have to be careful about back
> > compatibility.
>
> Good advice;
> Andy, you mentioned your machine was a "Pentium" (without any
> qualifications) so your machine doesn't have prefetch instructions.
>
> Momchil Velikov <velco at fadata dot bg> gave a nice list in his post.
>
> The exchange (xchg) instruction was included in the original 80386.
> It also issued a "bus lock" signal from the chip but as time passed,
> problems where found with its timing and its use for atomically handling
> symiphores was replaced with new instructions for that purpose.
>
> It has always done its register <-> memory thing correctly.

Thank you for the info.  This is _not_ in the XCHG description in the Intel 
Developer's manuals.  

My point, however, was that XCHG causes unavoidable processor locks in 
register-memory form.  This is unacceptable for any instruction used to speed 
up straight computation.  I passed on using it.

> Also, your "Pentium" (without any qualifications) does not have the
> "out of order execution, with register renaming, in multiple execution
> units" grown into its silcon.  Just ignore us on that subject.

ok.  for now.  :o)  
dumb statistic, fwiw: dual processor 500Mhz Celerons.  
My Mandrake 8.2 distro calls it a pentiumpro.  

> The easy way is to just keep on asking the list, some of us
> have been writing Intel-ASM since the I-4004 hit the
> street. (Myself included.)
>
> Mike

I will.  Thank you for the invitation.

Andy