This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: An unusual Performance approach using Synthetic registers
On Sunday 05 January 2003 10:39 pm, Andy Walker wrote:
>
> Simulated comparison of a loop end:
>
> w/o Synth
> ...
> mov eax,[StackSlot27] ; Load the increment from spill
> mov edx,[StackSlot23] ; Load the index -- spilled for lack of registers
> lea ecx,[eax + edx] ; Nicely optimized "add"
> mov edx,[StackSlot28]; Load the loop limit from spill
> cmp ecx,edx ; Compare the index to the loop limit.
> ...
>
> w/ Synth
> ...
> add ecx,[ebp -20] ; Add synthreg 27, the increment, to the index.
> cmp ecx,[ebp -16]; Compare the index to the loop limit in synthreg 28.
> ...
>
> This is my concept. Is it reality? I will not know until I have tried it.
>
Right!
Like I said elsewhere, the instruction set GCC generates for stack
slots SHOULD be greater than load/store or push/pop.
Andy, your approach of putting Synthetic Registers on the stack
frame has nothing to do with effects on the D-cache...
It should allow a quick and easy verification of what code GCC
would generate IF it where modified to code/use what are now
spill slots as local temporaries.
I also suspect that a larger example than you choose to show
will also have significantly fewer register stalls.
On the ia32 machines that do out-of-order execution with
register renaming in four or more execution units - the cycle
count of a major sized routine should be significantly different.
Keep at it. I think we will all learn something.
Mike