PowerPC Code generation (probably altivec related)

[Daniel Egger <degger at fhm dot edu>]

Hija,

I stumbled about some code generation oddity on powerpc-linux.
Consider the following code:

#include <altivec.h>

float test ()
{
  const vector float test = (vector float) {0.0, 0.0, 0.0, 0.0};
  static float store[4] __attribute__ ((aligned(16)));
  float buf;

  vec_st (test, 0, store);
  buf = store[0] + store[1] + store[2] + store[3];

  return buf;
}

Compiling that snippet with:
/opt/gcc/bin/gcc -O3 -c test.c -mabi=altivec -maltivec -save-temps

yields:

   0:   7c e0 42 a6     mfvrsave        r7
   4:   94 21 ff e0     stwu    r1,-32(r1)
   8:   64 e6 df ff     oris    r6,r7,57343
   c:   60 c0 f0 00     ori     r0,r6,61440
  10:   90 e1 00 1c     stw     r7,28(r1)
  14:   7c 00 43 a6     mtvrsave        r0
  18:   38 a0 00 00     li      r5,0
  1c:   3c 80 00 00     lis     r4,0
  20:   10 21 0c c4     vxor    v1,v1,v1
  24:   38 64 00 00     addi    r3,r4,0
  28:   7c 25 19 ce     stvx    v1,r5,r3
  2c:   c0 23 00 04     lfs     f1,4(r3)
  30:   c0 a4 00 00     lfs     f5,0(r4)  <======
  34:   c0 83 00 08     lfs     f4,8(r3)
  38:   ec 65 08 2a     fadds   f3,f5,f1
  3c:   c0 43 00 0c     lfs     f2,12(r3)
  40:   80 01 00 1c     lwz     r0,28(r1)
  44:   ec 03 20 2a     fadds   f0,f3,f4
  48:   ec 20 10 2a     fadds   f1,f0,f2
  4c:   7c 00 43 a6     mtvrsave        r0
  50:   38 21 00 20     addi    r1,r1,32
  54:   4e 80 00 20     blr

Please note that in the marked line a different register is
used for the load which is not a problem here since the
content is the same but shows up as a problem in code I'm
still trying to simplify where the load happens from a completely
wrong address.

Removing the static in the declaration of store will result
in the expected object code but trigger a different (altivec) code
generation problem for my application:

   0:   7c c0 42 a6     mfvrsave        r6
   4:   94 21 ff d0     stwu    r1,-48(r1)
   8:   64 c5 df ff     oris    r5,r6,57343
   c:   60 a0 f0 00     ori     r0,r5,61440
  10:   90 c1 00 2c     stw     r6,44(r1)
  14:   7c 00 43 a6     mtvrsave        r0
  18:   38 80 00 00     li      r4,0
  1c:   10 21 0c c4     vxor    v1,v1,v1
  20:   38 61 00 10     addi    r3,r1,16
  24:   7c 24 19 ce     stvx    v1,r4,r3
  28:   c0 21 00 14     lfs     f1,20(r1)
  2c:   c0 a1 00 10     lfs     f5,16(r1)
  30:   c0 01 00 18     lfs     f0,24(r1)
  34:   ec 85 08 2a     fadds   f4,f5,f1
  38:   c0 61 00 1c     lfs     f3,28(r1)
  3c:   80 01 00 2c     lwz     r0,44(r1)
  40:   ec 44 00 2a     fadds   f2,f4,f0
  44:   ec 22 18 2a     fadds   f1,f2,f3
  48:   7c 00 43 a6     mtvrsave        r0
  4c:   38 21 00 30     addi    r1,r1,48
  50:   4e 80 00 20     blr

-- 
Servus,
       Daniel