gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c

   1 /* { dg-do compile { target lp64 } } */
   2 /* { dg-options "-O2 -mdejagnu-cpu=power8" } */
   3 /* { dg-require-effective-target p8vector_hw } */
   4
   5 /* Test to verify that the vec_extract with constant element numbers can load
   6    SImode and fold the sign/extension into the load.  */
   7
   8 #include <altivec.h>
   9
  10 long long
  11 extract_sign_v4si_0 (vector int *p)
  12 {
  13   return vec_extract (*p, 0);           /* lwa, no extsw.  */
  14 }
  15
  16 long long
  17 extract_sign_v4si_1 (vector int *p)
  18 {
  19   return vec_extract (*p, 1);           /* lwa, no extsw.  */
  20 }
  21
  22 unsigned long long
  23 extract_uns_v4si_0 (vector unsigned int *p)
  24 {
  25   return vec_extract (*p, 0);           /* lwz, no rldicl.  */
  26 }
  27
  28 unsigned long long
  29 extract_uns_v4si_1 (vector unsigned int *p)
  30 {
  31   return vec_extract (*p, 0);           /* lwz, no rldicl.  */
  32 }
  33
  34 /* { dg-final { scan-assembler-times {\mlwa\M}   2 } } */
  35 /* { dg-final { scan-assembler-times {\mlwz\M}   2 } } */
  36 /* { dg-final { scan-assembler-not   {\mextsw\M}   } } */
  37 /* { dg-final { scan-assembler-not   {\mrldicl\M}  } } */