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(parent: 5ec8cf2) | patch
Add sign/zero conversions fro V4SI vec_extract
authorMichael Meissner <meissner@linux.ibm.com>
Mon, 17 Apr 2023 22:25:34 +0000 (18:25 -0400)
committerMichael Meissner <meissner@linux.ibm.com>
Mon, 17 Apr 2023 22:25:34 +0000 (18:25 -0400)
commit577ade1c244e73596489a6e7ba9a0f13f7dd16b6
tree552fd4c6433129d7ac811fbdbcbe139b06886f0btree
parent5ec8cf2151220c14043b19cdfee8e6fc1b85e49ccommit | diff
Add sign/zero conversions fro V4SI vec_extract

This patch adds combiner insns to fold in sign and zero extension of vec_extract
of V4SI with a constant element when expanding to DImode.

2023-04-17   Michael Meissner  <meissner@linux.ibm.com>

gcc/

* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.

gcc/testsuite/

* gcc.target/powerpc/vec-extract-mem-int-2.c: New test.
gcc/config/rs6000/vsx.md diff | blob | blame | history
gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c [new file with mode: 0644] blob
GNU Compiler Collection
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