Bug 90722 - ICE with __builtin_convertvector with -msve-vector-bits=256
Summary: ICE with __builtin_convertvector with -msve-vector-bits=256
Status: RESOLVED FIXED
Alias: None
Product: gcc
Classification: Unclassified
Component: target (show other bugs)
Version: 10.0
: P3 normal
Target Milestone: 10.0
Assignee: Not yet assigned to anyone
URL:
Keywords: ice-on-valid-code
Depends on:
Blocks:
 
Reported: 2019-06-03 11:54 UTC by prathamesh3492
Modified: 2020-01-20 21:01 UTC (History)
1 user (show)

See Also:
Host:
Target: aarch64-linux-gnu
Build:
Known to work:
Known to fail:
Last reconfirmed:


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Description prathamesh3492 2019-06-03 11:54:55 UTC
The following test-case:

typedef int v4si __attribute__((vector_size (4 * sizeof (int))));
typedef double v4df __attribute__((vector_size (4 * sizeof (double))));

void
f4 (v4df *x, v4si *y)
{
  *y = __builtin_convertvector (*x, v4si);
}

results in ICE with -O2 -march=armv8.2-a+sve -msve-vector-bits=256:

0xcddacd simplify_const_unary_operation(rtx_code, machine_mode, rtx_def*, machine_mode)
	../../gcc/gcc/simplify-rtx.c:1763
0xcd9c2a simplify_unary_operation(rtx_code, machine_mode, rtx_def*, machine_mode)
	../../gcc/gcc/simplify-rtx.c:873
0x13bca5a combine_simplify_rtx
	../../gcc/gcc/combine.c:5787
0x13bf1a6 subst
	../../gcc/gcc/combine.c:5727
0x13bf2bb subst
	../../gcc/gcc/combine.c:5590
0x13bf102 subst
	../../gcc/gcc/combine.c:5661
0x13c0568 try_combine
	../../gcc/gcc/combine.c:3420
0x13c66c6 combine_instructions
	../../gcc/gcc/combine.c:1306
0x13c66c6 rest_of_handle_combine
	../../gcc/gcc/combine.c:15068
0x13c66c6 execute
	../../gcc/gcc/combine.c:15113

because it hits following assert in simplify_const_unary_operation:
    gcc_assert (known_eq (GET_MODE_NUNITS (mode), n_elts));

GET_MODE_NUNITS (mode) == 8 and n_elts == 4 for the test-case.

Thanks,
Prathamesh
Comment 1 Andrew Pinski 2020-01-20 21:01:12 UTC
Works for me with the trunk so closing as fixed.

apinski@xeond:~/src/toolchain-10$ ./marvell-tools/bin/aarch64-marvell-linux-gnu-gcc 8881.c -S -O2 -march=armv8.2-a+sve -msve-vector-bits=256 -o -
        .arch armv8.2-a+crc+sve
        .file   "8881.c"
        .text
        .align  2
        .p2align 4,,11
        .global f4
        .type   f4, %function
f4:
.LFB0:
        .cfi_startproc
        ptrue   p0.b, vl32
        mov     z1.d, #0
        ld1d    z0.d, p0/z, [x0]
        fcvtzs  z1.s, p0/m, z1.d
        fcvtzs  z0.s, p0/m, z0.d
        uzp1    z0.s, z0.s, z1.s
        str     q0, [x1]
        ret
        .cfi_endproc
.LFE0:
        .size   f4, .-f4
        .ident  "GCC: (Marvell Development Version) 10.0.0 20200113 (experimental)"
        .section        .note.GNU-stack,"",@progbits