Created attachment 41679 [details] Testcase Missing memory side effect on __atomic_store using __ATOMIC_RELEASE. How to reproduce (atomic-fail.c attached): gcc atomic-fail.c -O2 -pthread -o atomic-fail ./atomic-fail Error: val != 1, missing memory side effect. The bug is not reproduced with __atomic_store using __ATOMIC_SEQ_CST. Probably this is similar to Bug80640.
Yes, it's a similar target-specific issue, and I've noticed it when writing a patch for PR 80640. At least x86 and s390 exhibit it. Perhaps it's better to fix it in the middle-end (i.e. expand) though, rather than require backends DTRT. I've submitted a partial patch for this issue here: https://gcc.gnu.org/ml/gcc-patches/2017-05/msg00786.html but at the moment both remain unreviewed. It also wouldn't fix this testcase, because I didn't notice that x86 used UNSPEC on the RHS (i.e. not the memory operand) of the store, so I added compiler barriers only for loads (more reason to fix it in expand, I guess). (the testcase formally invokes undefined behavior by entering an infinite loop without side effects)
Author: amonakov Date: Mon Sep 4 10:16:37 2017 New Revision: 251643 URL: https://gcc.gnu.org/viewcvs?rev=251643&root=gcc&view=rev Log: optabs: ensure atomic_load/stores have compiler barriers PR rtl-optimization/57448 PR target/67458 PR target/81316 * optabs.c (expand_atomic_load): Place compiler memory barriers if using atomic_load pattern. (expand_atomic_store): Likewise. testsuite/ * gcc.dg/atomic/pr80640-2.c: New testcase. * gcc.dg/atomic/pr81316.c: New testcase. Added: trunk/gcc/testsuite/gcc.dg/atomic/pr80640-2.c trunk/gcc/testsuite/gcc.dg/atomic/pr81316.c Modified: trunk/gcc/ChangeLog trunk/gcc/optabs.c trunk/gcc/testsuite/ChangeLog
Fixed.