Bug 66589 - AVX instruction set extension is not enabled by default for bdver2
Summary: AVX instruction set extension is not enabled by default for bdver2
Status: UNCONFIRMED
Alias: None
Product: gcc
Classification: Unclassified
Component: target (show other bugs)
Version: 5.1.0
: P3 minor
Target Milestone: ---
Assignee: Not yet assigned to anyone
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2015-06-18 17:35 UTC by Joseph Kogut
Modified: 2021-08-07 00:24 UTC (History)
1 user (show)

See Also:
Host:
Target:
Build:
Known to work: 10.3.0, 7.3.0, 7.5.0, 8.1.0, 8.5.0, 9.3.0, 9.4.0
Known to fail: 10.2.0, 6.4.0, 7.2.0
Last reconfirmed:

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Description Joseph Kogut 2015-06-18 17:35:05 UTC 
"gcc -march=bdver2 -Q --help=target" reports:

-mavx                                 [disabled]

When the extension is supported by the microarchitecture.
Comment 1 Jakub Jelinek 2015-06-18 17:58:33 UTC 
It is enabled:
      {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
        | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
        | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
        | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
        | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
Comment 2 Andrew Pinski 2021-08-07 00:24:26 UTC 
I don't why sometimes it shows up as enabled and other times it does not.