Created attachment 34588 [details] arm-none-eabi-gcc -O1 -S -o testcase.s testcase.c The testcase is submitted by Tim Pambor in bug #46164. But it's actually not the same bug with #46164. So I resubmitted the comments here. Command: arm-none-eabi-gcc -O1 -S -o testcase.s testcase.c The expected assembler code should be: mov r4, .L_temp mov r1, r4 ... mov r0, r0 @ r0 mov r1, r1 @ r1 mov r2, r2 @ r2 But GCC combined the insns, and the code is generated as: mov r4, .L_temp ... mov r0, r0 @ r0 mov r4, r4 @ r1 mov r2, r2 @ r2 Just "-O1" could reproduce this problem. The combine pass combined the user specified registers into inline-asm operation which caused this bug. There are three insns which are related to the user specified register "r1": (insn 98 97 40 3 (set (reg/v:SI 1 r1 [ b ]) (reg:SI 154 [ b ])) (insn 41 40 43 3 (set (reg/f:SI 148) (reg/v:SI 1 r1 [ b ])) (insn 43 41 45 3 (parallel [ (set (reg/v:SI 0 r0 [ ret ]) (asm_operands/v:SI ("mov %2, %2 mov %3, %3 mov %4, %4") ("=r") 0 [ (reg/v:SI 0 r0 [ a ]) (reg/v:SI 1 r1 [ b ]) (reg/v:SI 2 r2 [ c ]) (mem/c:QI (reg/f:SI 148) [0 MEM[(char *)&temp]+0 S1 A8]) The combine pass combine these insns as: (note 98 97 40 3 NOTE_INSN_DELETED) (note 41 40 43 3 NOTE_INSN_DELETED) (insn 43 41 45 3 (parallel [ (set (reg/v:SI 0 r0 [ ret ]) (asm_operands/v:SI ("mov %2, %2 mov %3, %3 mov %4, %4") ("=r") 0 [ (reg/v:SI 0 r0 [ a ]) (reg:SI 154 [ b ]) (reg/v:SI 2 r2 [ c ]) (mem/c:QI (reg:SI 154 [ b ]) [0 MEM[(char *)&temp]+0 S1 A8]) But actually 41+43 can be combined but 98+43 can not. Because if combining the 98+43, the user specified register will be replaced with a normal virtual register reg 154. It's not the user expected behavior.
Author: xguo Date: Wed Apr 22 07:21:35 2015 New Revision: 222306 URL: https://gcc.gnu.org/viewcvs?rev=222306&root=gcc&view=rev Log: gcc/ChangeLog: 2015-04-22 Hale Wang <hale.wang@arm.com> Terry Guo <terry.guo@arm.com> PR rtl-optimization/64818 * combine.c (can_combine_p): Don't combine user-specified register if it is in an asm input. gcc/testsuite/ChangeLog 2015-04-22 Hale Wang <hale.wang@arm.com> Terry Guo <terry.guo@arm.com> PR rtl-optimization/64818 * gcc.target/arm/pr64818.c: New test. Added: trunk/gcc/testsuite/gcc.target/arm/pr64818.c Modified: trunk/gcc/ChangeLog trunk/gcc/combine.c trunk/gcc/testsuite/ChangeLog
Author: halewang Date: Wed Jun 3 07:17:23 2015 New Revision: 224057 URL: https://gcc.gnu.org/viewcvs?rev=224057&root=gcc&view=rev Log: 2015-06-03 Hale Wang <hale.wang@arm.com> Backport from mainline r222306 2015-04-22 Hale Wang <hale.wang@arm.com> Terry Guo <terry.guo@arm.com> PR rtl-optimization/64818 * combine.c (can_combine_p): Don't combine user-specified register if it is in an asm input. Added: branches/ARM/embedded-4_9-branch/gcc/testsuite/gcc.target/arm/pr64818.c Modified: branches/ARM/embedded-4_9-branch/gcc/ChangeLog.arm branches/ARM/embedded-4_9-branch/gcc/combine.c
Author: belagod Date: Thu Dec 10 17:13:47 2015 New Revision: 231531 URL: https://gcc.gnu.org/viewcvs?rev=231531&root=gcc&view=rev Log: gcc/ChangeLog.arm: 2015-12-10 Tejas Belagod <tejas.belagod@arm.com> Backport from Mainline 2015-04-22 Hale Wang <hale.wang@arm.com> Terry Guo <terry.guo@arm.com> PR rtl-optimization/64818 * combine.c (can_combine_p): Don't combine user-specified register if it is in an asm input. gcc/testsuite/ChangeLog.arm: 2015-12-10 Tejas Belagod <tejas.belagod@arm.com> Backport from Mainline 2015-04-22 Hale Wang <hale.wang@arm.com> Terry Guo <terry.guo@arm.com> PR rtl-optimization/64818 * gcc.target/arm/pr64818.c: New test. Added: branches/ARM/embedded-5-branch/gcc/testsuite/gcc.target/arm/pr64818.c Modified: branches/ARM/embedded-5-branch/gcc/ChangeLog.arm branches/ARM/embedded-5-branch/gcc/combine.c branches/ARM/embedded-5-branch/gcc/testsuite/ChangeLog.arm
Fixed in r222306.