Bug 61633 - AArch64 SISD ASHR instruction split clobbers input register.
Summary: AArch64 SISD ASHR instruction split clobbers input register.
Status: RESOLVED FIXED
Alias: None
Product: gcc
Classification: Unclassified
Component: target (show other bugs)
Version: 4.9.0
: P3 normal
Target Milestone: 4.9.1
Assignee: mshawcroft
URL:
Keywords:
: 61665 (view as bug list)
Depends on:
Blocks:
 
Reported: 2014-06-27 15:46 UTC by mshawcroft
Modified: 2014-07-01 21:18 UTC (History)
1 user (show)

See Also:
Host:
Target: aarch64*-*-*
Build:
Known to work:
Known to fail:
Last reconfirmed: 2014-06-27 00:00:00


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Description mshawcroft 2014-06-27 15:46:21 UTC
The FFT code in Android AAC codec at -O2 is incorrectly compiled resulting in an infinite loop. I've failed to reduce the test case to something usable but the problem in the back end is clearly the define_splits associated with *aarch64_ashr_sisd_or_int_<mode>3.  Both of the splits inappropriately use one of the input operand register as a scratch pad for the negated shift operand.
Comment 1 mshawcroft 2014-06-30 07:55:31 UTC
Author: mshawcroft
Date: Mon Jun 30 07:54:59 2014
New Revision: 212137

URL: https://gcc.gnu.org/viewcvs?rev=212137&root=gcc&view=rev
Log:
[AArch64] Fix register clobber in, aarch64_ashr_sisd_or_int_<mode>3 split.

PR target/61633

The two split patterns associated with
aarch64_ashr_sisd_or_int_<mode>3 split the instruction into a NEG
followed by an SHL.  The split uses one of the input operands as a
scratch register to hold the output of the NEG resulting in register
corruption.

This patch adjusts the splits to use the output operand as the scratch
register.

2014-06-30  Marcus Shawcroft  <marcus.shawcroft@arm.com>

       PR target/61633
       * config/aarch64/aarch64.md (*aarch64_ashr_sisd_or_int_<mode>3):
       Add alternative; make early clobber.  Adjust both split patterns
       to use operand 0 as the working register.


Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/aarch64/aarch64.md
Comment 2 mshawcroft 2014-06-30 11:58:51 UTC
Author: mshawcroft
Date: Mon Jun 30 11:58:18 2014
New Revision: 212143

URL: https://gcc.gnu.org/viewcvs?rev=212143&root=gcc&view=rev
Log:
[AArch64] Fix register clobber in, aarch64_ashr_sisd_or_int_<mode>3 split.

        Backport from Mainline
        2014-06-30  Marcus Shawcroft  <marcus.shawcroft@arm.com>

        PR target/61633
        * config/aarch64/aarch64.md (*aarch64_ashr_sisd_or_int_<mode>3):
        Add alternative; make early clobber.  Adjust both split patterns
        to use operand 0 as the working register.


Modified:
    branches/gcc-4_9-branch/gcc/ChangeLog
    branches/gcc-4_9-branch/gcc/config/aarch64/aarch64.md
Comment 3 mshawcroft 2014-06-30 12:00:22 UTC
Fixed in trunk, back ported to 4.9 branch.
Comment 4 Andrew Pinski 2014-07-01 21:18:44 UTC
*** Bug 61665 has been marked as a duplicate of this bug. ***