In GCC's version of pmmintrin.h we have: #ifdef __SSE3__ #include <xmmintrin.h> #include <emmintrin.h> /* Additional bits in the MXCSR. */ #define _MM_DENORMALS_ZERO_MASK 0x0040 #define _MM_DENORMALS_ZERO_ON 0x0040 #define _MM_DENORMALS_ZERO_OFF 0x0000 #define _MM_SET_DENORMALS_ZERO_MODE(mode) \ _mm_setcsr ((_mm_getcsr () & ~_MM_DENORMALS_ZERO_MASK) | (mode)) #define _MM_GET_DENORMALS_ZERO_MODE() \ (_mm_getcsr() & _MM_DENORMALS_ZERO_MASK) ... and then SSE3 intrinsics. But those addtionnal MXCSR bits can be found, for example, on a k8 with only SSE2. Side note: they aren't guarded this way either in Intel headers.
Confirmed.
I guess that H.J. will know what shall we do here.
pmmintrin.h is for SSE3. I don't see anything wrong here. If someone wants to support SSE3 macros on some processors with SSE2, a new header file may be used.
So, wontfix.