The patch: [PR114810][LRA]: Recognize alternatives with lack of available registers for insn and demote them. Results in some ICE in the rvv.exp of RISC-V backend. ========= Summary of gcc testsuite ========= | # of unexpected case / # of unique unexpected case | gcc | g++ | gfortran | rv64gcv/ lp64d/ medlow | 1061 / 69 | 0 / 0 | - | make: *** [Makefile:1096: report-gcc-newlib] Error 1 Just pick one imm_loop_invariant-10.c as below. .../gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c:20:1: error: unrecognizable insn: (insn 265 0 0 (parallel [ (set (reg:RVVMF8QI 309 [239]) (unspec:RVVMF8QI [ (reg:SI 0 zero) ] UNSPEC_VUNDEF)) (clobber (scratch:SI)) ]) -1 (nil)) during RTL pass: reload …. gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c:20:1: internal compiler error: in extract_insn, at recog.cc:2812 0xa9d309 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*) ........../.././gcc/gcc/rtl-error.cc:108 0xa9d32b _fatal_insn_not_found(rtx_def const*, char const*, int, char const*) ........../.././gcc/gcc/rtl-error.cc:116 0xa9bc07 extract_insn(rtx_insn*) ........../.././gcc/gcc/recog.cc:2812 0x10e5ad2 ira_remove_insn_scratches(rtx_insn*, bool, _IO_FILE*, rtx_def* (*)(rtx_def*)) ........../.././gcc/gcc/ira.cc:5381 0x112868f remove_insn_scratches ........../.././gcc/gcc/lra.cc:2154 0x112868f lra_emit_move(rtx_def*, rtx_def*) ........../.././gcc/gcc/lra.cc:513 0x1136883 match_reload ........../.././gcc/gcc/lra-constraints.cc:1184 0x1142ae4 curr_insn_transform ........../.././gcc/gcc/lra-constraints.cc:4778 0x11443cb lra_constraints(bool) ........../.././gcc/gcc/lra-constraints.cc:5481 0x112b192 lra(_IO_FILE*, int) ........../.././gcc/gcc/lra.cc:2442 0x10e0e7f do_reload ........../.././gcc/gcc/ira.cc:5973 0x10e0e7f execute ........../.././gcc/gcc/ira.cc:6161 reproduced by below command: riscv64-unknown-elf-gcc -c -S gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c -march=rv32gcv -mabi=ilp32 -o -
The LRA patch has also been identified as the cause of similar failures in the PRU port (gcc.dg/pr71478.c): /cc1 -O2 pr71478.c -quiet pr71478.c: In function ‘foo’: pr71478.c:19:1: error: unable to find a register to spill 19 | } | ^ pr71478.c:19:1: error: this is the insn: (insn 15 33 30 2 (set (reg:SI 169 [orig:163 _11 ] [163]) (mult:SI (reg:SI 171) (reg:SI 172 [170]))) "pr71478.c":18:12 discrim 1 631 {mulsi3} (expr_list:REG_DEAD (reg:SI 172 [170]) (expr_list:REG_DEAD (reg:SI 171) (nil)))) during RTL pass: reload pr71478.c:19:1: internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 0x14fda20 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*) /home/jlaw/test/gcc/gcc/rtl-error.cc:108 0x12eff3a lra_split_hard_reg_for() /home/jlaw/test/gcc/gcc/lra-assigns.cc:1868 0x12e91fe lra(_IO_FILE*, int) /home/jlaw/test/gcc/gcc/lra.cc:2518 0x1291c6b do_reload /home/jlaw/test/gcc/gcc/ira.cc:5973 0x12920fa execute /home/jlaw/test/gcc/gcc/ira.cc:6161 Please submit a full bug report, with preprocessed source (by using -freport-bug). Please include the complete backtrace with any bug report. See <https://gcc.gnu.org/bugs/> for instructions. jlaw@x11-dpi:~/test/obj/pru/gcc/gcc$
Sorry for troubles. I've started to work on this PR. ETA for the fix is Monday.
No worries Vlad. At least for my tester I've got the LRA patch reverted. So I'm getting regular test results. Thanks for diving in and for the review work on the Rivai's team on subreg tracking in the allocator.
The master branch has been updated by Vladimir Makarov <vmakarov@gcc.gnu.org>: https://gcc.gnu.org/g:44e7855e4e817a7f5a1e332cd95e780e57052dba commit r15-436-g44e7855e4e817a7f5a1e332cd95e780e57052dba Author: Vladimir N. Makarov <vmakarov@redhat.com> Date: Mon May 13 10:12:11 2024 -0400 [PR115013][LRA]: Modify register starvation recognition My recent patch to recognize reg starvation resulted in few GCC test failures. The following patch fixes this by using more accurate starvation calculation and ignoring small reg classes. gcc/ChangeLog: PR rtl-optimization/115013 * lra-constraints.cc (process_alt_operands): Update all_used_nregs only for winreg. Ignore reg starvation for small reg classes.
So this seems to have fixed the RISC-V port. Thanks! I'm still seeing some problems on the PRU port though: Tests that now fail, but worked before (1 tests): pru-sim: gcc: gcc.dg/pr71478.c (test for excess errors) New tests that FAIL (1 tests): pru-sim: gcc: gcc.dg/pr71478.c (internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868) New tests that PASS (1 tests): pru-sim: gcc: gcc.dg/pr113982.c (test for excess errors)
Created attachment 58194 [details] tentative fix for PRU The PRU requires a further target adjustment to fix SMALL_REGISTER_CLASS_P. The attached patch fixes the dg.exp=pr71478.c regression. I'm doing full regression tests now, and will commit if there are no objections.
The master branch has been updated by Dimitar Dimitrov <dimitar@gcc.gnu.org>: https://gcc.gnu.org/g:fc559584fa5b1e101a4520e88a936246458d5a5d commit r15-493-gfc559584fa5b1e101a4520e88a936246458d5a5d Author: Dimitar Dimitrov <dimitar@dinux.eu> Date: Mon May 13 19:24:14 2024 +0300 pru: Implement TARGET_CLASS_LIKELY_SPILLED_P to fix PR115013 Commit r15-436-g44e7855e did not fix PR115013 for PRU because SMALL_REGISTER_CLASS_P is not returning an accurate value for the PRU backend. Word mode for PRU backend is defined as 8-bit, yet all ALU operations are preferred in 32-bit mode. Thus checking whether a register class contains a single word_mode register would not classify the actually single SImode register classes as small. This affected the multiplication source and destination register classes. Fix by implementing TARGET_CLASS_LIKELY_SPILLED_P to treat all register classes with SImode or smaller size as likely spilled. This in turn corrects the behaviour of SMALL_REGISTER_CLASS_P for PRU. PR rtl-optimization/115013 gcc/ChangeLog: * config/pru/pru.cc (pru_class_likely_spilled_p): Implement to mark classes containing one SImode register as likely spilled. (TARGET_CLASS_LIKELY_SPILLED_P): Define. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
Fixed.