Bug 113744 - Unnecessary "m" constraint in *adddi_4
Summary: Unnecessary "m" constraint in *adddi_4
Status: RESOLVED FIXED
Alias: None
Product: gcc
Classification: Unclassified
Component: target (show other bugs)
Version: 14.0
: P3 normal
Target Milestone: ---
Assignee: kong lingling
URL:
Keywords: missed-optimization
Depends on:
Blocks:
 
Reported: 2024-02-03 14:58 UTC by H.J. Lu
Modified: 2024-08-01 04:44 UTC (History)
5 users (show)

See Also:
Host:
Target: x86_64-*-* i?86-*-*
Build:
Known to work:
Known to fail:
Last reconfirmed: 2024-07-31 00:00:00


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Description H.J. Lu 2024-02-03 14:58:47 UTC
commit 7abcef725e40589553a079df9258ae094b811751
Author: Kong Lingling <lingling.kong@intel.com>
Date:   Wed Jan 18 17:23:29 2023 +0800

    [APX NDD] Support APX NDD for optimization patterns of add

has

@@ -6994,31 +7021,35 @@ (define_insn "*addsi_3_zext"
 (define_insn "*adddi_4"
   [(set (reg FLAGS_REG)
   (compare
-    (match_operand:DI 1 "nonimmediate_operand" "0")
-    (match_operand:DI 2 "x86_64_immediate_operand" "e")))
-   (clobber (match_scratch:DI 0 "=r"))]
+    (match_operand:DI 1 "nonimmediate_operand" "0,rm")
+    (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
+   (clobber (match_scratch:DI 0 "=r,r"))]
   "TARGET_64BIT
    && ix86_match_ccmode (insn, CCGCmode)"

But peephole which generates *adddi_4 only supports register as operand 2.
Comment 1 H.J. Lu 2024-02-03 15:00:37 UTC
Other *add patterns may have the same issue.
Comment 2 Hongtao Liu 2024-02-04 03:06:02 UTC
 7018; For comparisons against 1, -1 and 128, we may generate better code
 7019; by converting cmp to add, inc or dec as done by peephole2.  This pattern
 7020; is matched then.  We can't accept general immediate, because for
 7021; case of overflows,  the result is messed up.
 7022; Also carry flag is reversed compared to cmp, so this conversion is valid
 7023; only for comparisons not depending on it.
 7024

It sounds to me those peephole2 can be extended to memory operand since APX_NDD supports that. So it's not redudant m constraint in the pattern, but miss optimization in those peepholes.
Comment 3 kong lingling 2024-07-31 02:47:59 UTC
*add<mode>_4 and *adddi_4 are for shorter opcode from cmp to
inc/dec or add $128. But NDD code is longer than the cmp code,
so there is no need to support ndd.
Comment 4 Hongtao Liu 2024-07-31 04:30:46 UTC
Then please remove constraint from the pattern.
Comment 5 GCC Commits 2024-08-01 03:09:48 UTC
The master branch has been updated by Kong Lingling <konglin1@gcc.gnu.org>:

https://gcc.gnu.org/g:25dba615e3c191f0a7264538b6d260e91ca2624a

commit r15-2471-g25dba615e3c191f0a7264538b6d260e91ca2624a
Author: Lingling Kong <lingling.kong@intel.com>
Date:   Thu Aug 1 11:05:41 2024 +0800

    i386: Remove ndd support for *add<mode>_4 [PR113744]
    
    *add<mode>_4 and *adddi_4 are for shorter opcode from cmp to
    inc/dec or add $128. But NDD code is longer than the cmp code,
    so there is no need to support ndd.
    
    gcc/ChangeLog:
    
            PR target/113744
            * config/i386/i386.md (*add<mode>_4): Remove ndd support.
            (*adddi_4): Ditto.
    
    Co-Authored-By: Hu, Lin1 <lin1.hu@intel.com>
Comment 6 Hongtao Liu 2024-08-01 04:44:47 UTC
Fixed in GCC15.