I found this case in my riscv vector test case, and following is snippets of problematic RTL:


before register renamer :
=========================

(insn 64 62 109 4 (parallel [
            (set (reg:VNx32HI 104 v8 [orig:148 _30 ] [148])
                (unspec:VNx32HI [
                        (plus:VNx32HI (reg:VNx32HI 100 v4 [orig:149 _31 ] [149])
                            (zero_extend:VNx32HI (reg:VNx32QI 108 v12 [orig:159 _41 ] [159])))
                        (reg:SI 66 vl)
                    ] UNSPEC_USEVL))
            (use (reg:VNx32QI 67 vtype))
        ]) "/$GCC/lib/gcc/riscv64-unknown-linux-gnu/10.2.0/include/riscv_vector.h":1865:1 23384 {*wadduvnx32qi_wv_nosetvl}
     (nil))
(insn 109 64 67 4 (set (reg:VNx32HI 100 v4 [orig:147 _29 ] [147])
        (reg:VNx32HI 104 v8 [orig:148 _30 ] [148])) "/$GCC/lib/gcc/riscv64-unknown-linux-gnu/10.2.0/include/riscv_vector.h":2815:1 21247 {*movvnx32hi}
     (nil))
(insn 67 109 69 4 (parallel [
            (set (reg:VNx32HI 100 v4 [orig:147 _29 ] [147])
                (unspec:VNx32HI [
                        (plus:VNx32HI (mult:VNx32HI (zero_extend:VNx32HI (vec_duplicate:VNx32QI (reg:QI 10 a0 [184])))
                                (zero_extend:VNx32HI (reg:VNx32QI 98 v2 [orig:152 _34 ] [152])))
                            (reg:VNx32HI 100 v4 [orig:147 _29 ] [147]))
                        (reg:SI 66 vl)
                    ] UNSPEC_USEVL))
            (use (reg:VNx32QI 67 vtype))
        ]) "/$GCC/lib/gcc/riscv64-unknown-linux-gnu/10.2.0/include/riscv_vector.h":2815:1 27941 {*umaddvnx32qivnx32hi4_scalar_nosetvl}
     (expr_list:REG_EQUAL (unspec:VNx32HI [
                (plus:VNx32HI (mult:VNx32HI (zero_extend:VNx32HI (reg:VNx32QI 98 v2 [orig:152 _34 ] [152]))
                        (const_vector:VNx32HI [
                                (const_int 2 [0x2])
                            ]))
                    (reg:VNx32HI 104 v8 [orig:148 _30 ] [148]))
                (reg:SI 66 vl)
            ] UNSPEC_USEVL)
        (nil)))


after register renamer :
========================

(insn 64 62 109 4 (parallel [
            (set (reg:VNx32HI 100 v4 [orig:148 _30 ] [148])
                (unspec:VNx32HI [
                        (plus:VNx32HI (reg:VNx32HI 116 v20 [orig:149 _31 ] [149])
                            (zero_extend:VNx32HI (reg:VNx32QI 108 v12 [orig:159 _41 ] [159])))
                        (reg:SI 66 vl)
                    ] UNSPEC_USEVL))
            (use (reg:VNx32QI 67 vtype))
        ]) "/$GCC/lib/gcc/riscv64-unknown-linux-gnu/10.2.0/include/riscv_vector.h":1865:1 23384 {*wadduvnx32qi_wv_nosetvl}
     (expr_list:REG_DEAD (reg:VNx32QI 108 v12 [orig:159 _41 ] [159])
        (expr_list:REG_DEAD (reg:VNx32HI 100 v4 [orig:149 _31 ] [149])
            (nil))))
(insn:TI 109 64 67 4 (set (reg:VNx32HI 124 v28 [orig:147 _29 ] [147])
        (reg:VNx32HI 100 v4 [orig:148 _30 ] [148])) "/$GCC/lib/gcc/riscv64-unknown-linux-gnu/10.2.0/include/riscv_vector.h":2815:1 21247 {*movvnx32hi}
     (expr_list:REG_DEAD (reg:VNx32HI 104 v8 [orig:148 _30 ] [148])
        (nil)))
(insn 67 109 69 4 (parallel [
            (set (reg:VNx32HI 124 v28 [orig:147 _29 ] [147])
                (unspec:VNx32HI [
                        (plus:VNx32HI (mult:VNx32HI (zero_extend:VNx32HI (vec_duplicate:VNx32QI (reg:QI 10 a0 [184])))
                                (zero_extend:VNx32HI (reg:VNx32QI 114 v18 [orig:152 _34 ] [152])))
                            (reg:VNx32HI 124 v28 [orig:147 _29 ] [147]))
                        (reg:SI 66 vl)
                    ] UNSPEC_USEVL))
            (use (reg:VNx32QI 67 vtype))
        ]) "/$GCC/lib/gcc/riscv64-unknown-linux-gnu/10.2.0/include/riscv_vector.h":2815:1 27941 {*umaddvnx32qivnx32hi4_scalar_nosetvl}
     (expr_list:REG_DEAD (reg:VNx32HI 104 v8 [orig:148 _30 ] [148])
        (expr_list:REG_DEAD (reg:VNx32QI 98 v2 [orig:152 _34 ] [152])
            (expr_list:REG_DEAD (reg:VNx32QI 98 v2 [orig:152 _34 ] [152])
                (expr_list:REG_EQUAL (unspec:VNx32HI [
                            (plus:VNx32HI (mult:VNx32HI (zero_extend:VNx32HI (reg:VNx32QI 98 v2 [orig:152 _34 ] [152]))
                                    (const_vector:VNx32HI [
                                            (const_int 2 [0x2])
                                        ]))
                                (reg:VNx32HI 104 v8 [orig:148 _30 ] [148]))
                            (reg:SI 66 vl)
                        ] UNSPEC_USEVL)
                    (nil))))))


From rnreg pass RTL dump as following, it will try to tie chains in a move instruction for a single output.
So we can keep same register (dest and source) in this move instruction, it means
insn 64 renamed as v4, and insn 109 should keep v4 as noop move instruction.

Register v8 in insn 64deferring rescan insn with uid = 64.
deferring rescan insn with uid = 109.
, renamed as v4
Register v4 in insn 109deferring rescan insn with uid = 109.
deferring rescan insn with uid = 67.
deferring rescan insn with uid = 69.
, renamed as v28