Re: powerpc & unaligned block moves with fp registers

[degger at fhm dot edu]

On 10 Nov, dewar@gnat.com wrote:

> This is too pessimistic. For example, on Power, the penalty for a
> misligned access is far less than this.

I assumed we're still at PowerPCs and it's not far away from what I
said; I just checked back with the UM of the 7400 and it shows basically
the same. 

> Yes, it very much depends on the architecture, but your generalization
> is not accurate (and far too pessimistic) for many cases.

Pessimistic or not, we should try to avoid misaligned accesses on any
cost since they are in a lucky case at least magnitude slower.

> I don't have the figures for latest chips in the Pentium and Athlon
> series, but I would be very surprised if the penalty is as much as a
> few dozen cycles (on earlier chips it was about one clock).

Recent processors have optimisations for memory accesses which only
work for aligned read/writes. That means that they're a lot slower
than older CPUs when those requirements are not met.

--
Servus,
       Daniel