MIPS & register allocation question

[Richard Sandiford]

Steve Ellcey <steve.ellcey@imgtec.com> writes:
> On Wed, 2013-02-27 at 22:28 +0000, Richard Sandiford wrote:
>> FWIW, after seeing that, I tried the patch below.  Disabling
>> ADJUST_REG_ALLOC_ORDER seemed to be a very mixed bag sizewise though --
>> certainly not the consistent win that I hoped -- and I wasn't set up to
>> do proper speed testing.  In the end I'm afraid I just let it drop.
>> 
>> Thanks,
>> Richard
>
> I'll try your patch on some of my benchmarks and see what happens.

Thanks.

> One interesting thing I have noticed (sizewise) is that not using t0-t7
> at all in MIPS16 code resulted in a code size reduction of around 1%.

Hmm, yes indeed.  Certainly not what I'd have expected.  And an
impressive difference for such a small change.

Have you managed to track down why?  Naively, a spill into a non-MIPS16
GPR ought to be no worse than a spill to the stack, so I wonder what's
going wrong.

It'll be interesting to see how things look after the transition to LRA.

Richard