ralloc UNSPEC vs UNSPEC_VOLATILE
Hariharan Sandanagobalane
hariharans@picochip.com
Mon Oct 18 10:40:00 GMT 2010
Hello,
Picochip has communication instructions that allow one array element to
pass data to another. There are 3 such instructions PUT/GET/TSTPORT.
Currently, all three of these use UNSPEC_VOLATILE side-effect
expressions to make sure they don't get reordered with respect to each
other.
There were quite a few testcases where virtual registers assigned to
communication instructions were being spilled, even in functions where
register pressure is not very high. I looked at the data flow
information and it looks like the virtual registers involved in these
UNSPEC_VOLATILE operations are marked to interfere with every live range.
To avoid unnecessary register spill due to UNSPEC_VOLATILE rtl
expressions, i converted these patterns to use UNSPEC expressions. But,
the live ranges of virtual registers involved here still show the same
characteristics as above. Is this right? Why does the live range of a
virtual register involved in UNSPEC operation be marked to interfere
with live ranges of all the other virtual registers?
I tried looking into the code, but i am not sure how UNSPEC patterns are
handled.
Please let me know if i am missing something here.
Cheers
Hari
PS: I attach a concrete testcase, with dumps of sched and ira. In the
mainline case, it is virtual register 36. In unspec-patch case, it is
virtual register 37. I attach the unspec patch to picochip port, which
you can apply to mainline if you would like to test.
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