Problem with memory alignment for 64 byte moves

Neil Hickey neil@petapath.com
Thu Dec 16 14:54:00 GMT 2010


Hi Ian

Thanks for the response.

All of those flags are set correctly, though it is still emitting
loads and stores 4 byte aligned and not 8. I'm trying to get the
compiler to combine two 4 byte loads in to a single 8 byte load as it
is more efficient on this architecture, so I'm guessing because the
objects being loaded are actually 4 byte aligned, the compiler is
matching for this alignment.

There was a similar email about combining loads/stores which people
seemed to suggest wasn't possible. Is there any way to do this other
than writing a machine reorg pass which will split up loads and stores
it notices are misaligned?

On 3 December 2010 19:34, Ian Lance Taylor <iant@google.com> wrote:
> Neil Hickey <neil@petapath.com> writes:
>
>> I'm porting gcc to a new architecture and I'm allowing use of movdi
>> instructions as the processor allows 8 byte loads. The processor
>> however requires 8 byte loads and stores to be naturally aligned, yet
>> gcc seems to be emitting loads and stores that are 4 byte aligned. How
>> can I make sure that gcc will only emit 8 byte loads and stores if it
>> knows the address, which can be in a register, is 8 byte aligned?
>
> Define STRICT_ALIGNMENT to 1.
>
> Make sure that BIGGEST_ALIGNMENT, BIGGEST_FIELD_ALIGNMENT,
> MAX_STACK_ALIGNMENT, DATA_ALIGNMENT, etc. are correct.
>
> Ian
>



More information about the Gcc mailing list