Problem with memory alignment for 64 byte moves

[Ian Lance Taylor]

Neil Hickey <neil@petapath.com> writes:

> I'm porting gcc to a new architecture and I'm allowing use of movdi
> instructions as the processor allows 8 byte loads. The processor
> however requires 8 byte loads and stores to be naturally aligned, yet
> gcc seems to be emitting loads and stores that are 4 byte aligned. How
> can I make sure that gcc will only emit 8 byte loads and stores if it
> knows the address, which can be in a register, is 8 byte aligned?

Define STRICT_ALIGNMENT to 1.

Make sure that BIGGEST_ALIGNMENT, BIGGEST_FIELD_ALIGNMENT,
MAX_STACK_ALIGNMENT, DATA_ALIGNMENT, etc. are correct.

Ian