Doubt about filling delay slot

[Boris Boesler]

Am 03.04.2008 um 16:22 schrieb Mohamed Shafi:
> On Thu, Apr 3, 2008 at 7:35 PM, Ian Lance Taylor <iant@google.com>  
> wrote:
>> "Mohamed Shafi" <shafitvm@gmail.com> writes:
>>
>>> Now imagine that i have 3 patterns : Pattern A with two instructions
>>> in its template, Pattern B and Pattern C with only one  
>>> instruction in
>>> its template.
>>> When it comes to filling the call instruction delay slot if slot  
>>> 1 is
>>> filled with Pattern A then there is no need to fill slot 2. But  
>>> if its
>>> filled with Pattern C or Pattern B, then slot 2 should be filled  
>>> with
>>> Pattern B or Pattern C, but not Pattern A.
>>> Will i be able to do this in the back-end?
>>
>>  Ah, OK.  It's easy enough to say that you can't put pattern A in  
>> slot
>>  2.  But there is no way to say that if pattern A is in slot 1, then
>>  slot 2 is not available.
>>
> Ok i guess you are saying that this is not possible.
> But then this should be something that all the targets should deal
> with. How are they doing it?
>
> May be i can set the attribute "slottable" as 'no' for patterns with 3
> or more instructions and in DBR_OUTPUT_SEQEND or in
> TARGET_MACHINE_DEPENDENT_REORG check the delay slots and reorder the
> instructions if the slots are filled with 3 instructions ?
>
> Are there any other solutions?

  Workaround: never place Pattern/instruction A in a delay slot
Correct implementation: rewrite your machine description such that  
every instruction emit at most one assembler instruction

Boris