How to make use of instruction scheduling to improve performance?

Ian Lance Taylor
Sat Jul 28 16:04:00 GMT 2007

"吴曦" <> writes:

> there are some questions after I read the source code today.
> 1st. if I add the instrumentation before 2nd scheduling; will gcc emit
> an insn which will be output as a ld instruction later? If this could
> happen, some ld instruction may not be instrumented...

No, gcc won't introduce any new memory load or store instructions
after the prologue and epilogue instructions are threaded.  It may
still move them around or eliminate them, though.

> 2nd. to identify ld/st instruction (memory access op), I want to
> modify gen_rtx_SET, the method is that, if I find SRC or DST is an
> memory operand in gen_rtx_SET, then add instrumentation code before
> and after the insn to emit. Will this method work? Besides, if some
> false positives occur, how to correct them (I don't have some very
> clear idea.)

Modifying gen_rtx_SET is probably not the right way to go.  That is
used in many places throughout the RTL passes.  Not all of those
places are going to be able to cope with the new instructions you want
to add.


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