How to make use of instruction scheduling to improve performance?

吴曦 wu.andrew.xi@gmail.com
Sat Jul 28 15:19:00 GMT 2007


2007/7/28, 吴曦 <wu.andrew.xi@gmail.com>:
> 2007/7/28, Ramana Radhakrishnan <ramana.r@gmail.com>:
> > Hi,
> >
> >
> > On 7/28/07, 吴曦 <wu.andrew.xi@gmail.com> wrote:
> > > > > > > I am working on gcc 4.1.1 and itanium2 architecture. I instrumented
> > > > > > > each ld and st instruction in final_scan_insn() by looking at the insn
> > > > > > > template (These instrumentations are used to do some security checks).
> > > > > > > These instrumentations incur high performance overhead when running
> > > > > > > specint benchmarks. However, these instrumentations contain high
> > > > > > > dependencies between instructions so that I want to use instruction
> > > > > > > scheduling to improve the performance.
> > > > > > >     In the current implementation, the instrumentations are emitted as
> > > > > > > assembly instructions (not insns). What should I do to make use of the
> > > > > > > instruction scheduler?
> > > > > >
> > > > > > If I understand your description, you are adding instrumentation code,
> > > > > > and you want to expose that code to the scheduler.  What you need to
> > > > > > do in that case is to add the code as RTL instructions before the
> > > > > > scheduling pass runs.  You will need to figure out the RTL which will
> > > > > > do what you want.  Then you will need to insert it around the
> > > > >                                ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > > > > > instructions which you want to instrument.  You will probably want to
> > > > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > > > > Before the second scheduling pass, how to identify that one insn will
> > > > > be output as a load instruction (or store instruction)? In the final,
> > > > > i use get_insn_template() to do this matching. Can I use the same
> > > > > method before the second scheduling pass? If not, would you mind
> > > > > giving some hints? thx
> > > >
> > > > Please send followups to the mailing list, not just to me.  Thanks.
> > > >
> > > > You should just match on the RTL.  I don't know enough about the
> > > > Itanium to tell you precisely what to look for.  But, for example, you
> > > > might look for
> > > >    s = single_set (PATTERN (insn));
> > > >    if (s != NULL && (MEM_P (SET_SRC (s) || MEM_P (SET_DEST (s)))))
> > > >      ...
> > > >
> > > > Ian
> > > >
> > >
> > > Thanks. I observe that the 2nd instruction scheduling happens after
> > > the local and global allocation. However, in my instrumentation, I
> > > need several registers to do computation, can I allocate registers to
> > > do computation in the instrumentation code just before the 2nd
> > > instruction scheduling? If so, would you mind giving some hints on the
> > > interfaces that I could make use of.
> >
> > Generally you should be able to create new temporaries for such
> > calculations before register allocation / reload . Otherwise you might
> > have to resort to reserving a couple of registers in your ABI for such
> > computations if you wanted these generated after reload (you could
> > have a split that did that after reload but where in the function do
> > you want to insert the instrumentation code ?)
> >
> > From what you are indicating - there isn't enough detail about where
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > in the function body you are inserting such instrumentation code  -
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> thx, As I have in indicated, I want to add instrumentations for each
> ld and st instruction in one function on itanium. (In my current
> implementation, I also instrument cmp and mv instructions on itanium).
> for example, for a ld instruction in the original program:
>                         ld rX=[rY]
> I want to instrument it as
>                         instrumentation prologue
>                         ld rX=[rY]
>                         instrumentation epilogue
> currently, to identify such ld instruction, I put my instrumentation
> in final, and use get_insn_template() to see what instruction this
> insn will be output as.
>
> To summarize, as I want to expose my instrumentation to instruction
> scheduling, following work should be done:
>                       1. identify that one insn will be output as a
> ld instruction
>                       2. allocate register to do the instrumentation
> calculation (in my current implementation, I use dedicated register to
> do this.)
>                       3. emit the prepared instrumentation insn
> >
> > If you are doing such instrumentation in the prologue or epilogue of a
> > function, you could choose to use gen_reg_rtx to obtain a temporary
> > register.
> >
> > So typically obtain a temporary register in the following manner
> >  rtx tmp_reg = gen_reg_rtx (<machine>mode);
> >
> > Use the tmp_reg in whatever instruction you want to generate using the
> > corresponding register as one of the operands .  For these you might
> > want to use the corresponding gen_*** named functions .
> >
> > cheers
> > Ramana
> >
> >
> >
> >
> >
> >
> >
> >
> > >    Besides,  what happens if I move the insertion of instrumentation
> > > before register allocation,  or even before the 1st scheduling pass,
> > > can I identify load/store instructions that early?
> > >
> >
> >
> > --
> > Ramana Radhakrishnan
> >
>
> Thanks for your hints.
>
Hi
there are some questions after I read the source code today.
1st. if I add the instrumentation before 2nd scheduling; will gcc emit
an insn which will be output as a ld instruction later? If this could
happen, some ld instruction may not be instrumented...

2nd. to identify ld/st instruction (memory access op), I want to
modify gen_rtx_SET, the method is that, if I find SRC or DST is an
memory operand in gen_rtx_SET, then add instrumentation code before
and after the insn to emit. Will this method work? Besides, if some
false positives occur, how to correct them (I don't have some very
clear idea.)

Any hints ? thx


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