Incorrect DFA scheduling of output dependency.

[Nathan Sidwell]

Daniel,
> I am using the DFA scheduler to implement VLIW scheduling for a 16-bit 
> DSP. Recently I have come across an apparent bug in the scheduler. 
> Consider the following sequence of instructions, with DFA scheduling 
> turned off:
> 

> Now the DFA scheduler has grouped the four instructions into two VLIW 
> packets. However, the first of these packets contains an instruction 
> which writes to R3, and which reads from R3. Thus, the wrong value of R3 
> is shifted into R5. It appears that the output dependency of the initial 
> instruction is not being respected?

something is wrong with your scheduler description, but I know not what :)
You need to tell the scheduler about the bundling, how are you doing that?

nathan

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