Incorrect DFA scheduling of output dependency.

[Daniel Towner]

Hi all,

I am using the DFA scheduler to implement VLIW scheduling for a 16-bit 
DSP. Recently I have come across an apparent bug in the scheduler. 
Consider the following sequence of instructions, with DFA scheduling 
turned off:

_L11:
        COPY.0 0,R3
        LSL.0 R3,2,R5
        ADD.0 R3,1,R3
        ADD.0 R5,FP,R5

        // etc...

(note that destination operands come last, sources come first)

To begin with, this is rather a strange sequence - a register is initialised to 0, and then various operations performed on that register - I haven't figured out why constant propogation doesn't make a better job of this. Anyway, with DFA scheduling turned on, I get the following code instead:

_L11:

        COPY.0 0,R3     \
        LSL.1 R3,2,R5

        ADD.0 R3,1,R3   \
        ADD.1 R5,FP,R5

        // etc...

Now the DFA scheduler has grouped the four instructions into two VLIW packets. However, the first of these packets contains an instruction which writes to R3, and which reads from R3. Thus, the wrong value of R3 is shifted into R5. It appears that the output dependency of the initial instruction is not being respected?

Any ideas?

thanks,

dan.

============================================================================
Daniel Towner
picoChip Designs Ltd., Riverside Buildings, 108, Walcot Street, BATH,
BA1 5BG
daniel.towner@picochip.com
07786 702589