Load insn register restrictions

[Geert Bosch]

On Apr 12, 2004, at 16:22, Paul Brook wrote:
> I'm trying to add a new doubleword load instruction to the ARM 
> backend. It has
> the restriction that the index register must not be one of the 
> destination
> registers. For example ldrd r0, [r2 + r3] is valid, but ldrd r0, 
> [r2+r0] is
> not.
>
> I can't figure out how to express this in the machine description.
> Any suggestions?

Isn't this the '&' (earlyclobber) operand constraint?