Load insn register restrictions

[David Edelsohn]

>>>>> Paul Brook writes:

Paul> I'm trying to add a new doubleword load instruction to the ARM backend. It has 
Paul> the restriction that the index register must not be one of the destination 
Paul> registers. For example ldrd r0, [r2 + r3] is valid, but ldrd r0, [r2+r0] is 
Paul> not.

Paul> I can't figure out how to express this in the machine description.
Paul> Any suggestions?

	The early clobber constraint modifier might help or you have to
accept any register allocation and then drop to a splitter if the illegal
allocation occurs, which you can test with reg_overlap_mentioned_p().

David