GCC for 8051 based architectures

[tm_gccmail@mail.kloo.net]

On Fri, 11 Jul 2003, Julia Nilsson wrote:

> The problem with accumulator based architecture or
> harvard architecture where data memory and program
> memory are seperately addressed by different buses, is
> that memory operations are heavy also generating
> memory offset takes lots of instructions.
> 
> load Dptr
> add offset
> store Dptr
> << access memory from Dptr >>
> sub offset
> store Dptr
> 
> If each insn is executed in one cycle and there is no
> pipelining (which is the case for most of the
> microcontrollers) then we have 6 insns for memory
> read!!

Yes, the 8051 instruction set was not really designed for 
compiler-generated code. It was designed in an era when hand 
assembly was more common.

> I looked at sdcc but it is not fully ANSI compliant.
> Moreover the level of optimizations supported are also
> not so good.

Most compiler optimizations require a reasonable number of registers to
work efficiently, so even if the optimizations are supported, they
may not work well on the 8051 anyway.

> ~J

Toshi