arm instruction generate

[james chen]

Hi, I am using GCC 2.95( ARM target ) in my test
board, and the test boardbased in samsung
S3C2400X01(ARM920T core).  but there is a bug in it,
seebelows:

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 If the cache is turned on and there is an LDM
instruction (load multiple) ofprecisely two items from
a noncachedregion, then the second item may not be
loaded correctly.So, for example, LDMIA r0,{r1,r2}
from non-cacheable area is not allowed.But, LDMIA
r0,{r1,r2,r3} from noncacheablearea is allowed because
the number of items is not 2.In assembly code, the
software workaround was simply to ensure that
therewere no LDM instructions whichload only 2 values.
In compiled C code, LDM may be used only for
stacksave/restore operation, double typevariable
load/store and etc. But, we think there is no problem
if the Cstack area and C variable area iscacheable
area.

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will you help me to change GCC to avoid this
bug?Thanks in advance!
Best Regards,
james

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